Memory array capable of performing byte erase operation

• US 9,847,133 B2
• Filed: 05/10/2016
• Issued: 12/19/2017
• Est. Priority Date: 01/19/2016
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Lai, Tsung-Mu, Chen, Chih-Hsin, Wang, Shih-Chen, Po, Chen-Hao
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Bashar, Mohammed A
• Application Number:
  US15/150,440
• Publication Number:
  US 20170206970A1
• Time in Patent Office: 588 Days
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell

Abstract

A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.

Claims

1. A memory array, comprising:

a plurality of memory pages, each memory page comprising a plurality of memory bytes, each memory byte comprising a plurality of memory cells, and each memory cell comprising;

a floating gate module comprising;

a floating gate transistor having a first terminal, a second terminal and a floating gate;

a source transistor having a first terminal coupled to a source line, a second terminal coupled to the first terminal of the floating gate transistor, and a control terminal coupled to a word line; and

a bit transistor having a first terminal coupled to the second terminal of the floating gate transistor, a second terminal coupled to a bit line, and a control terminal coupled to the word line;

a control element having a body terminal coupled to a control line, a first terminal coupled to the body terminal, a second terminal coupled to the body terminal, and a control terminal coupled to the floating gate; and

an erase element having a first terminal coupled to an erase line, a second terminal coupled to the first terminal of the erase element, a body terminal coupled to the first terminal of the erase element, and a control terminal coupled to the floating gate;

wherein;

memory bytes of a same column are coupled to a same erase line;

memory bytes of different columns are coupled to different erase lines;

during a program operation of the memory cell;

the control line is at a first voltage;

the erase line is at a second voltage;

the word line is at a third voltage;

the source line is at a fourth voltage; and

the bit line is at the fourth voltage;

the first voltage is greater than the second voltage, the second voltage is greater than the third voltage, and the third voltage is greater than the fourth voltage;

a difference between the second voltage and the fourth voltage is greater than half of a difference between the first voltage and the fourth voltage; and

a difference between the third voltage and the fourth voltage is smaller than half of the difference between the first voltage and the fourth voltage.

2. The memory array of claim 1, wherein:

memory cells of a same memory page are coupled to a same control line; and

memory cells of different memory pages are coupled to different control lines.

3. The memory array of claim 1, wherein:

memory cells of a same memory page are coupled to a same word line; and

memory cells of different memory pages are coupled to different word lines.

4. The memory array of claim 1, wherein:

memory cells of the same column are coupled to a same source line and a same bit line; and

memory cells of different columns are coupled to different source lines and different bit lines.

5. The memory array of claim 1, wherein:

during the program operation of the memory cell;

an erase line coupled to an unselected memory cell in a same memory page as the memory cell is at the second voltage;

a source line coupled to the unselected memory cell is at the third voltage; and

a bit line coupled to the unselected memory cell is at the third voltage.

6. The memory array of claim 1, wherein:

during the program operation of the memory cell;

a control line coupled to an unselected memory cell in an unselected memory page but in a same column as the memory cell is at the third voltage; and

a word line coupled to the unselected memory cell is at the third voltage.

7. A memory array, comprising:

a plurality of memory pages, each memory page comprising a plurality of memory bytes, each memory byte comprising a plurality of memory cells, and each memory cell comprising;

a floating gate module comprising;

a floating gate transistor having a first terminal, a second terminal and a floating gate;

a source transistor having a first terminal coupled to a source line, a second terminal coupled to the first terminal of the floating gate transistor, and a control terminal coupled to a word line; and

a bit transistor having a first terminal coupled to the second terminal of the floating gate transistor, a second terminal coupled to a bit line, and a control terminal coupled to the word line;

a control element having a body terminal coupled to a control line, a first terminal coupled to the body terminal, a second terminal coupled to the body terminal, and a control terminal coupled to the floating gate; and

an erase element having a first terminal coupled to an erase line, a second terminal coupled to the first terminal of the erase element, a body terminal coupled to the first terminal of the erase element, and a control terminal coupled to the floating gate;

wherein;

memory bytes of a same column are coupled to a same erase line;

memory bytes of different columns are coupled to different erase lines;

during an erase operation of the memory cell;

the erase line is at a fifth voltage;

the control line is at a fourth voltage;

the word line is at a third voltage;

the source line is at the third voltage; and

the bit line is at the third voltage; and

the fifth voltage is greater than the third voltage, and the third voltage is greater than the fourth voltage.

8. The memory array of claim 7, wherein:

during the erase operation of the memory cell;

an erase line coupled to an unselected memory cell in a same memory page as the memory cell is at a sixth voltage;

a source line coupled to the unselected memory cell is at the third voltage; and

a bit line coupled to the unselected memory cell is at the third voltage;

the fifth voltage is greater than the sixth voltage, and the sixth voltage is greater than the fourth voltage; and

a difference between the sixth voltage and the fourth voltage is smaller than half of a difference between the fifth voltage and the fourth voltage.

9. The memory array of claim 7, wherein:

during the erase operation of the memory cell,

a control line coupled to an unselected memory cell in a different memory page from the memory cell is at a seventh voltage; and

a word line coupled to the unselected memory cell is at the third voltage;

the fifth voltage is greater than the seventh voltage, and the seventh voltage is greater than the fourth voltage; and

a difference between the seventh voltage and the fourth voltage is greater than half of a difference between the fifth voltage and the fourth voltage.