Method to reduce program disturbs in non-volatile memory cells
First Claim
1. A circuit, comprising:
- a memory array including,a plurality of memory cells, each comprising at least a non-volatile memory (NVM) transistor, arranged in rows and columns, wherein gates of the NVM transistors of memory cells in a same row couple to and share a global wordline; and
a programmable control circuitry coupled to the memory array, wherein the programmable control circuitry includes a voltage control circuitry configured to provide,a first voltage to a first global wordline in a first row of the memory array, and a second voltage to source-drain paths of memory cells in a first column of the memory array to apply a first bias voltage to the NVM transistor in a selected memory cell to program the selected memory cell, anda third voltage to source-drain paths of memory cells in a second column of the memory array.
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Abstract
A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.
39 Citations
20 Claims
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1. A circuit, comprising:
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a memory array including, a plurality of memory cells, each comprising at least a non-volatile memory (NVM) transistor, arranged in rows and columns, wherein gates of the NVM transistors of memory cells in a same row couple to and share a global wordline; and a programmable control circuitry coupled to the memory array, wherein the programmable control circuitry includes a voltage control circuitry configured to provide, a first voltage to a first global wordline in a first row of the memory array, and a second voltage to source-drain paths of memory cells in a first column of the memory array to apply a first bias voltage to the NVM transistor in a selected memory cell to program the selected memory cell, and a third voltage to source-drain paths of memory cells in a second column of the memory array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of operating a memory circuit, comprising:
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coupling a positive voltage to a first global wordline in a first row of a memory array of memory cells and coupling a negative voltage to first ends of source-drain paths of memory cells in a first column of the memory array to apply a first bias voltage to a non-volatile memory transistor in a selected memory cell to program the selected memory cell; and coupling a voltage having a magnitude less than the negative voltage to a second global wordline in a second row of the memory array and coupling an inhibit voltage to first ends of source-drain paths of memory cells in a second column of the memory array. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. The method of 11, further comprising:
coupling second ends of the source-drain paths of the memory cells in the first and second columns to a floating voltage.
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19. A memory array, comprising:
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a plurality of memory cells arranged in rows and columns, wherein each memory cell includes a non-volatile memory (NVM) transistor, wherein memory cells in a same row share a global wordline, and wherein first ends of memory cells in a same column are coupled to a same bitline, and second ends of the memory cells in the same column are configured to be coupled to a floating voltage, wherein during programming of a first memory cell associated with a first row and a first column, a positive voltage is applied to a first global wordline associated with the first row and a negative voltage is applied to a first bit line associated with the first column to apply a first bias voltage to a NVM transistor in the first memory cell, while a negative marginal voltage, which has a magnitude less than the negative voltage, is applied to a second global wordline associated with an unselected second row for programming, and an inhibited voltage is applied to a second bitline associated with an unselected second column for programming to minimize a second bias voltage applied to memory cells in the unselected second row and column for programming. - View Dependent Claims (20)
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Specification