TSV formation processes using TSV-last approach

• US 9,847,255 B2
• Filed: 04/08/2016
• Issued: 12/19/2017
• Est. Priority Date: 07/12/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jing-Cheng, Lin, Yung-Chi, Yang, Ku-Feng
• Primary Examiner(s): Vu, David
• Application Number:
  US15/094,207
• Publication Number:
  US 20160225668A1
• Time in Patent Office: 620 Days
• Field of Search: 438 55, 438106, 438107, 438113, 438124, 438125, 438126, 438127
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]

Abstract

A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad.

Claims

1. A method comprising:

forming an isolation region extending into a semiconductor substrate underlying an Inter-Layer Dielectric (ILD), wherein a bottom surface of the isolation region is at a first intermediate level between a top surface and a bottom surface of the semiconductor substrate;

etching the ILD and the isolation region to form an opening in the ILD and the isolation region;

filling the opening with a conductive material to form a landing pad; and

forming a Through-Substrate Via (TSV) extending from a back surface of the semiconductor substrate to electrically couple to the landing pad.

2. The method of claim 1, wherein the opening extends to a second intermediate level between the top surface of the semiconductor substrate and the bottom surface of the isolation region, and the forming the TSV comprises:

etching the semiconductor substrate and a bottom portion of the isolation region to expose a bottom surface of the landing pad.

3. The method of claim 1 further comprising forming a dielectric liner extending into the opening, wherein the conductive material is formed on the dielectric liner.

4. The method of claim 1, wherein the isolation region comprises a top portion encircling a portion of the landing pad.

5. The method of claim 1, wherein during the etching the ILD and the isolation region, the isolation region is etched through.

6. The method of claim 5, wherein after the etching the ILD and the isolation region, a portion of the semiconductor substrate directly underlying the opening is further etched.

7. The method of claim 1 further comprising, after the landing pad is formed and before the TSV is formed, forming metal bumps on a front side of the semiconductor substrate.

8. A method comprising:

forming an isolation region extending into a semiconductor substrate, with the isolation region formed from a front side of the semiconductor substrate;

forming a conductive pad extending from the front side of the semiconductor substrate into the isolation region;

etching the semiconductor substrate from a backside of the semiconductor substrate to form an opening in the semiconductor substrate, wherein the conductive pad is exposed through the opening; and

filling a conductive material into the opening to form a through-substrate via in the semiconductor substrate.

9. The method of claim 8 further comprising:

forming an Inter-Layer Dielectric (ILD) over the semiconductor substrate, wherein the isolation region extends from a bottom surface of the ILD into the semiconductor substrate.

10. The method of claim 9 further comprising etching the ILD, wherein the conductive pad comprises a portion filling an opening in the ILD.

11. The method of claim 8, wherein the forming the conductive pad comprises forming a conductive barrier layer, and forming a copper-containing region over the conductive barrier layer.

12. The method of claim 8, wherein the conductive pad stops at an intermediate level between a top surface and a bottom surface of the isolation region.

13. The method of claim 8, wherein the conductive pad penetrates through the isolation region.

14. The method of claim 8 further comprising forming a dielectric liner into the opening, wherein the conductive material is formed on the dielectric liner.

15. A method comprising:

forming an isolation region extending into a semiconductor substrate;

forming a transistor at a top surface of the semiconductor substrate;

forming an Inter-Layer Dielectric (ILD) over the semiconductor substrate, with a portion of the ILD at a same level as a portion of a gate electrode of the transistor;

etching the ILD and the isolation region to form a first opening;

filling the first opening with a first conductive material to form a conductive pad;

etching the semiconductor substrate from backside to form a second opening, with the conductive pad revealed through the second opening; and

filling the second opening with a first conductive material to form a through-substrate via.

16. The method of claim 15 further comprising forming a gate contact plug over and electrically coupled to the gate electrode, wherein the ILD has a top surface coplanar with a top surface of the gate contact plug, with the conductive pad having a top surface coplanar with the top surface of the ILD.

17. The method of claim 15 further comprising:

forming a dielectric liner extending into the first opening, wherein the first conductive material is formed on the dielectric liner; and

further etching the dielectric liner when the semiconductor substrate is etched-through from the backside.

18. The method of claim 15, wherein the forming the conductive pad comprises:

forming a conductive barrier layer extending into the first opening; and

filling a copper-containing material over the conductive barrier layer.

19. The method of claim 18, wherein the through-substrate via lands on the conductive barrier layer.

20. The method of claim 15, wherein the isolation region fully encircles the conductive pad.