Reducing risk of punch-through in FinFET semiconductor structure

• US 9,847,333 B2
• Filed: 02/23/2016
• Issued: 12/19/2017
• Est. Priority Date: 03/09/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Lim, Kwanyong, Akarvardar, Murat Kerem
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US15/051,420
• Publication Number:
  US 20160268260A1
• Time in Patent Office: 665 Days
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence

Abstract

Reducing a chance of punch-through in a FinFET structure includes providing a substrate, creating a blanket layer of semiconductor material with impurities therein over the substrate, masking a portion of the blanket layer, creating epitaxial semiconductor material on an unmasked portion of the structure, removing the mask, and etching the structure to create n-type raised structure(s) and p-type raised structure(s), a bottom portion of the raised structure(s) being surrounded by isolation material. A middle portion of the raised structure(s) includes a semiconductor material with impurities therein, the middle portion extending across the raised structure(s), and a top portion including a semiconductor material lacking added impurities.

Claims

1. A semiconductor structure, comprising:

a substrate; and

at least one semiconductor fin coupled to the substrate, a bottom portion of the at least one semiconductor fin being surrounded by isolation material;

wherein a middle portion of the at least one semiconductor fin comprises a semiconductor material with impurities therein, wherein the middle portion extends across the at least one semiconductor fin, wherein a top portion of the semiconductor fin comprises a semiconductor material lacking added impurities, wherein the semiconductor material with impurities therein comprises epitaxial semiconductor material, wherein the semiconductor structure comprises a n-type region and a p-type region, and wherein the epitaxial semiconductor material with impurities therein comprises boron-doped epitaxial silicon germanium.

2. The semiconductor structure of claim 1, wherein the at least one semiconductor fin comprises a n-type fin and a p-type fin, wherein the semiconductor structure is silicon-based, and wherein a middle portion of the p-type fin comprises phosphorous-doped silicon.

3. The semiconductor structure of claim 2, wherein the phosphorous-doped silicon comprises phosphorous-doped epitaxial silicon.

4. The semiconductor structure of claim 1, further comprising a gate surrounding a top portion of the at least one semiconductor fin.

5. A semiconductor structure, comprising:

a substrate;

at least one semiconductor fin coupled to the substrate, a bottom portion of the at least one semiconductor fin being surrounded by isolation material; and

wherein a middle portion of the at least one semiconductor fin comprises a semiconductor material with impurities therein, wherein the middle portion extends across the at least one semiconductor fin, wherein a top portion of the semiconductor fin comprises a semiconductor material lacking added impurities, wherein the at least one semiconductor fin comprises a n-type fin and a p-type fin, wherein the semiconductor structure is silicon-based, and wherein the top portion of the p-type fin comprises epitaxial silicon germanium lacking added impurities.

6. A semiconductor structure, comprising:

a substrate; and

at least one semiconductor fin coupled to the substrate, a bottom portion of the at least one semiconductor fin lacking added impurities being surrounded by isolation material; and

wherein a middle portion of the at least one semiconductor fin comprises a semiconductor material with impurities therein, wherein the middle portion extends across the at least one semiconductor fin, and wherein a top portion of the semiconductor fin comprises a semiconductor material lacking added impurities.

7. The semiconductor structure of claim 6, wherein the at least one semiconductor fin comprises a n-type fin and a p-type fin, wherein the semiconductor structure is silicon-based, and wherein a middle portion of the p-type fin comprises arsenic-doped silicon.

8. The semiconductor structure of claim 7, wherein the arsenic-doped silicon comprises arsenic-doped epitaxial silicon.

9. The semiconductor structure of claim 6, wherein the semiconductor material with impurities therein comprises epitaxial semiconductor material.

10. The semiconductor structure of claim 9, wherein the semiconductor structure comprises a n-type region and a p-type region, and wherein the epitaxial semiconductor material with impurities therein comprises boron-doped epitaxial silicon germanium.

11. The semiconductor structure of claim 6, wherein the at least one semiconductor fin comprises a n-type fin and a p-type fin, wherein the semiconductor structure is silicon-based, and wherein a middle portion of the p-type fin comprises phosphorous-doped silicon.

12. The semiconductor structure of claim 11, wherein the phosphorous-doped silicon comprises phosphorous-doped epitaxial silicon.