Stacked nanosheet field-effect transistor with diode isolation

• US 9,847,391 B1
• Filed: 04/05/2017
• Issued: 12/19/2017
• Est. Priority Date: 04/05/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Zang, Hui, Lee, Jae Gon
• Primary Examiner(s): Tobergte, Nicholas
• Application Number:
  US15/479,801
• Time in Patent Office: 258 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor. A substrate is provided that has a first conductivity type. A first semiconductor layer having a second conductivity type is formed on the substrate. A second semiconductor layer having the first conductivity type is formed on the first semiconductor layer. A field-effect transistor is formed that includes a fin having a plurality of nanosheet channel layers arranged in a vertical stack on the second semiconductor layer, and a gate structure wrapped about the nanosheet channel layers. The first semiconductor layer defines a first p-n junction with a portion of the substrate, and the second semiconductor layer defines a second p-n junction with the first semiconductor layer. The first p-n junction and the second p-n junction are arranged in vertical alignment with the gate structure and the nanosheet channel layers.

Claims

1. A structure comprising:

a layer stack including a first semiconductor layer having a first conductivity type and a second semiconductor layer having a second conductivity type, the first semiconductor layer arranged vertically to define a first p-n junction with the second semiconductor layer; and

a field-effect transistor on the first semiconductor layer, the field-effect transistor including a fin with a plurality of nanosheet channel layers arranged in a vertical stack and a gate structure wrapped about the nanosheet channel layers,

wherein the first p-n junction is arranged in vertical alignment with the gate structure and the nanosheet channel layers.

2. The structure of claim 1 further comprising:

a first trench isolation region extending through the first semiconductor layer and the first p-n junction; and

a second trench isolation region extending through the first semiconductor layer and the first p-n junction, the second trench isolation region spaced horizontally from the first trench isolation region,

wherein the first p-n junction is arranged horizontally between the first trench isolation region and the second trench isolation region.

3. The structure of claim 2 wherein the second semiconductor layer is a semiconductor substrate.

4. The structure of claim 2 wherein the layer stack includes a third semiconductor layer having the first conductivity type, the second semiconductor layer is vertically arranged between the first semiconductor layer and the third semiconductor layer, and the third semiconductor layer defines a second p-n junction with the second semiconductor layer.

5. The structure of claim 4 wherein the first trench isolation region and the second trench isolation region each extend through the second semiconductor layer and the second p-n junction into the third semiconductor layer, and the second p-n junction is arranged horizontally between the first trench isolation region and the second trench isolation region.

6. The structure of claim 4 wherein the third semiconductor layer is a semiconductor substrate.

7. The structure of claim 4 wherein the third semiconductor layer is a well in a semiconductor substrate.

8. The structure of claim 4 wherein the first trench isolation region and the second trench isolation region extend to a first depth relative to a top surface of the first semiconductor layer, the second p-n junction is located at a second depth relative to the top surface of the first semiconductor layer, and the second depth is greater than the first depth.

9. The structure of claim 2 wherein the field-effect transistor includes a first source/drain region and a second source/drain region, the gate structure and the nanosheet channel layers are arranged horizontally between the first source/drain region and the second source/drain region, the first source/drain region is arranged in vertical alignment with the first trench isolation region, and the second source/drain region is arranged in vertical alignment with the second trench isolation region.

10. The structure of claim 1 wherein the second semiconductor layer is a semiconductor substrate.

11. The structure of claim 1 wherein the layer stack includes a third semiconductor layer having the first conductivity type, the second semiconductor layer is vertically arranged between the first semiconductor layer and the third semiconductor layer, and the third semiconductor layer defines a second p-n junction with the second semiconductor layer.

12. The structure of claim 11 wherein the third semiconductor layer is a semiconductor substrate.

13. The structure of claim 11 wherein the third semiconductor layer is a well in a semiconductor substrate.

14. A method comprising:

forming a layer stack including a first semiconductor layer having a first conductivity type and a second semiconductor layer having a second conductivity type, the first semiconductor layer arranged vertically to define a first p-n junction with the second semiconductor layer; and

forming a field-effect transistor on the first semiconductor layer, the field-effect transistor including a fin with a plurality of nanosheet channel layers arranged in a vertical stack and a gate structure wrapped about the nanosheet channel layers,

wherein the first p-n junction is arranged in vertical alignment with the gate structure and the nanosheet channel layers.

15. The method of claim 14 further comprising:

forming a first trench isolation region extending through the first semiconductor layer and the first p-n junction; and

forming a second trench isolation region extending through the first semiconductor layer and the first p-n junction,

wherein the second trench isolation region is spaced horizontally from the first trench isolation region, and the first p-n junction is arranged horizontally between the first trench isolation region and the second trench isolation region.

16. The method of claim 15 wherein the layer stack includes a third semiconductor layer having the first conductivity type, the second semiconductor layer is vertically arranged between the first semiconductor layer and the third semiconductor layer, and the third semiconductor layer defining a second p-n junction with the second semiconductor layer.

17. The method of claim 16 wherein the first trench isolation region and the second trench isolation region each extend through the second semiconductor layer and the second p-n junction into the third semiconductor layer, and the second p-n junction is arranged horizontally between the first trench isolation region and the second trench isolation region.

18. The method of claim 16 wherein the first trench isolation region and the second trench isolation region extend to a first depth relative to a top surface of the first semiconductor layer, the second p-n junction is located at a second depth relative to the top surface of the first semiconductor layer, and the second depth is greater than the first depth.

19. The method of claim 14 wherein the layer stack includes a third semiconductor layer having the first conductivity type, the second semiconductor layer is vertically arranged between the first semiconductor layer and the third semiconductor layer, and the third semiconductor layer defines a second p-n junction with the second semiconductor layer.

20. The method of claim 19 wherein the third semiconductor layer is a semiconductor substrate, or a well in the semiconductor substrate.