Semiconductor device and manufacturing method thereof

• US 9,847,396 B2
• Filed: 03/18/2016
• Issued: 12/19/2017
• Est. Priority Date: 11/07/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Akimoto, Kengo, Kawae, Daisuke
• Primary Examiner(s): Payen, Marvin
• Assistant Examiner(s): JOY, JEREMY J
• Application Number:
  US15/074,287
• Publication Number:
  US 20160204270A1
• Time in Patent Office: 641 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/84 Ohmic electrodes, e.g. source or drain electrodes

Abstract

A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Claims

1. A semiconductor device comprising:

a first substrate;

a first conductive layer over the first substrate;

a first insulating layer over the first conductive layer;

a second conductive layer and a third conductive layer over the first insulating layer;

a first metal oxide layer over the second conductive layer;

a second metal oxide layer over the third conductive layer;

an oxide semiconductor layer over the first insulating layer, the first metal oxide layer, and the second metal oxide layer;

a first oxide layer in contact with a side surface of the second conductive layer;

a second oxide layer in contact with a side surface of the third conductive layer;

a second insulating layer over the oxide semiconductor layer;

a pixel electrode over the second insulating layer and electrically connected to the third conductive layer;

a first alignment film over the pixel electrode;

a liquid crystal layer over the first alignment film; and

a second substrate over the liquid crystal layer,

wherein the first metal oxide layer is between the oxide semiconductor layer and the second conductive layer,

wherein the second metal oxide layer is between the oxide semiconductor layer and the third conductive layer,

wherein the oxide semiconductor layer comprises indium, zinc, and oxygen,

wherein the first metal oxide layer and the second metal oxide layer comprise indium, zinc, and oxygen,

wherein the pixel electrode comprises indium, zinc, and oxygen, and

wherein the second conductive layer and the third conductive layer comprise copper.

2. The semiconductor device according to claim 1, wherein the first metal oxide layer and the second metal oxide layer comprise gallium.

3. The semiconductor device according to claim 1, wherein each of the second conductive layer and the third conductive layer has a step in a lower portion thereof.

4. The semiconductor device according to claim 1, wherein each of the first oxide layer and the second oxide layer is a natural oxide film.

5. The semiconductor device according to claim 1, wherein the second conductive layer and the third conductive layer are in contact with the first insulating layer.

6. The semiconductor device according to claim 1, wherein the second insulating layer is in contact with the second conductive layer and the third conductive layer.

7. The semiconductor device according to claim 1,

wherein an angle between a surface of the first substrate and the side surface of the second conductive layer is greater than or equal to 20°

and less than 90°

, and

wherein an angle between the surface of the first substrate and the side surface of the third conductive layer is greater than or equal to 20° and

less than 90°

.

8. The semiconductor device according to claim 1, wherein the pixel electrode is in contact with the second insulating layer.

9. The semiconductor device according to claim 1, comprising a counter electrode provided with a second alignment film between the liquid crystal layer and the second substrate.

10. A semiconductor device comprising:

a first substrate;

a first conductive layer over the first substrate;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer over the first insulating layer;

a first metal oxide layer and a second metal oxide layer in contact with the oxide semiconductor layer;

a second conductive layer in contact with the first metal oxide layer;

a third conductive layer in contact with the second metal oxide layer;

a first oxide layer in contact with a side surface of the second conductive layer;

a second oxide layer in contact with a side surface of the third conductive layer;

a second insulating layer over the oxide semiconductor layer;

a pixel electrode over the second insulating layer and electrically connected to the third conductive layer;

a first alignment film over the pixel electrode;

a liquid crystal layer over the first alignment film; and

a second substrate over the liquid crystal layer,

wherein the first metal oxide layer is between the oxide semiconductor layer and the second conductive layer,

wherein the second metal oxide layer is between the oxide semiconductor layer and the third conductive layer,

wherein the oxide semiconductor layer comprises indium, zinc, and oxygen,

wherein the first metal oxide layer and the second metal oxide layer comprise indium, zinc, and oxygen,

wherein the pixel electrode comprises indium, zinc, and oxygen, and

wherein the second conductive layer and the third conductive layer comprise copper.

11. The semiconductor device according to claim 10, wherein the first metal oxide layer and the second metal oxide layer comprise gallium.

12. The semiconductor device according to claim 10, wherein each of the first oxide layer and the second oxide layer is a natural oxide film.

13. The semiconductor device according to claim 10, wherein the second conductive layer and the third conductive layer are in contact with the first insulating layer.

14. The semiconductor device according to claim 10, wherein the second insulating layer is in contact with the second conductive layer and the third conductive layer.

15. The semiconductor device according to claim 10,

wherein an angle between a surface of the first substrate and the side surface of the second conductive layer is greater than or equal to 20°

and less than 90°

, and

wherein an angle between the surface of the first substrate and the side surface of the third conductive layer is greater than or equal to 20° and

less than 90°

.

16. The semiconductor device according to claim 10, wherein the pixel electrode is in contact with the second insulating layer.

17. The semiconductor device according to claim 10, comprising a counter electrode provided with a second alignment film between the liquid crystal layer and the second substrate.

18. A semiconductor device comprising:

a first substrate;

a first conductive layer over the first substrate;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer over the first insulating layer;

a first metal oxide layer and a second metal oxide layer in contact with the oxide semiconductor layer;

a second conductive layer in contact with the first metal oxide layer;

a third conductive layer in contact with the second metal oxide layer;

a first oxide layer in contact with a side surface of the second conductive layer;

a second oxide layer in contact with a side surface of the third conductive layer;

a second insulating layer over the oxide semiconductor layer;

a pixel electrode over the second insulating layer and electrically connected to the third conductive layer;

a first alignment film over the pixel electrode;

a liquid crystal layer over the first alignment film; and

a second substrate over the liquid crystal layer,

wherein the first metal oxide layer is between the oxide semiconductor layer and the second conductive layer,

wherein the second metal oxide layer is between the oxide semiconductor layer and the third conductive layer,

wherein the oxide semiconductor layer comprises indium, zinc, and oxygen,

wherein the first metal oxide layer and the second metal oxide layer comprise indium, zinc, and oxygen,

wherein the pixel electrode comprises indium, zinc, and oxygen,

wherein the second conductive layer and the third conductive layer comprise copper, and

wherein each of the second conductive layer and the third conductive layer has a step in a lower portion thereof.

19. The semiconductor device according to claim 18, wherein the first metal oxide layer and the second metal oxide layer comprise gallium.

20. The semiconductor device according to claim 18, wherein each of the first oxide layer and the second oxide layer is a natural oxide film.

21. The semiconductor device according to claim 18, wherein the second conductive layer and the third conductive layer are in contact with the first insulating layer.

22. The semiconductor device according to claim 18, wherein the second insulating layer is in contact with the second conductive layer and the third conductive layer.

23. The semiconductor device according to claim 18,

wherein an angle between a surface of the first substrate and the side surface of the second conductive layer is greater than or equal to 20°

and less than 90°

, and

wherein an angle between the surface of the first substrate and the side surface of the third conductive layer is greater than or equal to 20° and

less than 90°

.

24. The semiconductor device according to claim 18, wherein the pixel electrode is in contact with the second insulating layer.

25. The semiconductor device according to claim 18, comprising a counter electrode provided with a second alignment film between the liquid crystal layer and the second substrate.