Semiconductor device

• US 9,847,430 B2
• Filed: 11/03/2016
• Issued: 12/19/2017
• Est. Priority Date: 06/15/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US15/342,333
• Publication Number:
  US 20170054031A1
• Time in Patent Office: 411 Days
• Field of Search: None
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04886 by partitioning the display area of the touch-screen or the surface of the digitising tablet into independently controllable areas, e.g. virtual keyboards or menus
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 31/03762 including only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/103 the potential barrier being of the PN homojunction type
• CPC Class Codes: H10K 59/40 OLEDs integrated with touch screens
• CPC Class Codes: H10K 59/65 OLEDs integrated with inorganic image sensors

Abstract

High field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a bottom-gate transistor including an oxide semiconductor layer, an oxide semiconductor layer functioning as a current path (channel) of the transistor is sandwiched between oxide semiconductor layers having lower carrier densities than the oxide semiconductor layer. In such a structure, the channel is formed away from the interface of the oxide semiconductor stacked layer with an insulating layer in contact with the oxide semiconductor stacked layer, i.e., a buried channel is formed.

Claims

1. A semiconductor device comprising:

a transistor;

a photodiode electrically connected to the transistor; and

a first insulating layer between the transistor and the photodiode,

wherein the transistor comprises;

an oxide semiconductor stack comprising;

a first oxide semiconductor layer;

a second oxide semiconductor layer on and in contact with the first oxide semiconductor layer; and

a third oxide semiconductor layer in contact with a top surface of the second oxide semiconductor layer;

a gate electrode layer overlapping with the oxide semiconductor stack with a second insulating layer interposed therebetween; and

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor stack,

wherein a difference between a Fermi level and a bottom of a conduction band in the second oxide semiconductor layer is smaller than those in the first oxide semiconductor layer and the third oxide semiconductor layer, and

wherein the first insulating layer comprises a first insulating film having a blocking property against hydrogen.

2. The semiconductor device according to claim 1,

wherein the first insulating layer is positioned over the transistor, and

wherein the photodiode is positioned over the first insulating layer.

3. The semiconductor device according to claim 1, wherein the photodiode is electrically connected to the gate electrode layer of the transistor.

4. The semiconductor device according to claim 1,

wherein the second insulating layer is positioned over the gate electrode layer, and

wherein the oxide semiconductor stack is positioned over the second insulating layer.

5. The semiconductor device according to claim 1, wherein the first insulating film is a silicon nitride film.

6. The semiconductor device according to claim 1,

wherein the first insulating layer comprises a second insulating film in contact with the oxide semiconductor stack, and

wherein the first insulating film is in contact with the second insulating film.

7. The semiconductor device according to claim 6,

wherein the first insulating film is a silicon nitride film, and

wherein the second insulating film is a silicon oxide film.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor stack is positioned over the gate electrode layer with the second insulating layer interposed therebetween.

9. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer comprises an impurity imparting an n-type conductivity.

30. The semiconductor device according to claim 1, wherein the third oxide semiconductor layer is in contact with a side surface of the second oxide semiconductor layer.

10. A semiconductor device comprising:

a transistor;

a photodiode electrically connected to the transistor; and

a first insulating layer between the transistor and the photodiode,

wherein the transistor comprises;

an oxide semiconductor stack comprising;

a first oxide semiconductor layer;

a second oxide semiconductor layer on and in contact with the first oxide semiconductor layer; and

a third oxide semiconductor layer in contact with a top surface of the second oxide semiconductor layer;

a gate electrode layer overlapping with the oxide semiconductor stack with a second insulating layer interposed therebetween; and

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor stack,

wherein a difference between a Fermi level and a bottom of a conduction band in the second oxide semiconductor layer is smaller than those in the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein the photodiode comprises an amorphous silicon film, and

wherein the first insulating layer comprises a first insulating film having a blocking property against hydrogen.

11. The semiconductor device according to claim 10,

wherein the first insulating layer is positioned over the transistor, and

wherein the photodiode is positioned over the first insulating layer.

12. The semiconductor device according to claim 10, wherein the photodiode is electrically connected to the gate electrode layer of the transistor.

13. The semiconductor device according to claim 10,

wherein the second insulating layer is positioned over the gate electrode layer, and

wherein the oxide semiconductor stack is positioned over the second insulating layer.

14. The semiconductor device according to claim 10, wherein the first insulating film is a silicon nitride film.

15. The semiconductor device according to claim 10,

wherein the first insulating layer comprises a second insulating film in contact with the oxide semiconductor stack, and

wherein the first insulating film is in contact with the second insulating film.

16. The semiconductor device according to claim 15,

wherein the first insulating film is a silicon nitride film, and

wherein the second insulating film is a silicon oxide film.

17. The semiconductor device according to claim 10, wherein the oxide semiconductor stack is positioned over the gate electrode layer with the second insulating layer interposed therebetween.

18. The semiconductor device according to claim 10, wherein the second oxide semiconductor layer comprises an impurity imparting an n-type conductivity.

31. The semiconductor device according to claim 10, wherein the third oxide semiconductor layer is in contact with a side surface of the second oxide semiconductor layer.

19. An electronic device comprising:

a display portion having a touch-input function and, capable of displaying a button used for the touch-input function on the display portion,

wherein the display portion comprises;

a transistor;

a photodiode electrically connected to the transistor; and

a first insulating layer between the transistor and the photodiode,

wherein the transistor comprises;

an oxide semiconductor stack comprising;

a first oxide semiconductor layer;

a second oxide semiconductor layer on and in contact with the first oxide semiconductor layer; and

a third oxide semiconductor layer in contact with a top surface of the second oxide semiconductor layer;

a gate electrode layer overlapping with the oxide semiconductor stack with a second insulating layer interposed therebetween; and

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor stack,

wherein a difference between a Fermi level and a bottom of a conduction band in the second oxide semiconductor layer is smaller than those in the first oxide semiconductor layer and the third oxide semiconductor layer, and

wherein the first insulating layer comprises a first insulating film having a blocking property against hydrogen.

20. The electronic device according to claim 19, wherein the photodiode comprises an amorphous silicon film.

21. The electronic device according to claim 19,

wherein the first insulating layer is positioned over the transistor, and

wherein the photodiode is positioned over the first insulating layer.

22. The electronic device according to claim 19, wherein the photodiode is electrically connected to the gate electrode layer of the transistor.

23. The electronic device according to claim 19,

wherein the second insulating layer is positioned over the gate electrode layer, and

wherein the oxide semiconductor stack is positioned over the second insulating layer.

24. The electronic device according to claim 19, wherein the first insulating film is a silicon nitride film.

25. The electronic device according to claim 19,

wherein the first insulating layer comprises a second insulating film in contact with the oxide semiconductor stack, and

wherein the first insulating film is in contact with the second insulating film.

26. The electronic device according to claim 25,

wherein the first insulating film is a silicon nitride film, and

wherein the second insulating film is a silicon oxide film.

27. The electronic device according to claim 19, wherein the oxide semiconductor stack is positioned over the gate electrode layer with the second insulating layer interposed therebetween.

28. The electronic device according to claim 19, wherein the second oxide semiconductor layer comprises an impurity imparting an n-type conductivity.

29. The electronic device according to claim 19, wherein the electronic device is a table comprising the display portion incorporated in a housing.

32. The electronic device according to claim 19, wherein the third oxide semiconductor layer is in contact with a side surface of the second oxide semiconductor layer.