Regulator using smart partitioning

• US 9,847,705 B2
• Filed: 03/15/2013
• Issued: 12/19/2017
• Est. Priority Date: 08/06/2012
• Status: Active Grant

• Current Assignee: Peter Oaklander
• Original Assignee: Peter Oaklander
• Inventors: Oaklander, Peter
• Primary Examiner(s): Zhang, Jue
• Assistant Examiner(s): DANG, TRINH Q
• Application Number:
  US13/841,939
• Publication Number:
  US 20140035628A1
• Time in Patent Office: 1,740 Days
• Field of Search: 363147, 323271, 323272, 323282, 323283, 327541, 700298, 361600
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/14 Arrangements for reducing ripples from dc input or output
• CPC Class Codes: H02M 1/44 Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 7/537 using semiconductor devices only, e.g. single switched pulse inverters
• CPC Class Codes: H03K 17/063 in field-effect transistor switches

Abstract

A disclosed apparatus includes a converter for receiving a supply and regulating a load. The converter uses a gate driver that is controlled by a controller via a control loop. The control loop controls the converter in response to a feedback signal. The controller is located on a first integrated circuit and the gate driver is located on as second integrated circuit. A process geometry of the first integrated circuit is finer than a process geometry of the second integrated circuit.

Claims

1. An apparatus comprising:

a converter for regulating a DC voltage provided from a power supply to a load;

a control loop for controlling the converter;

a smart gate driver coupled to the power supply, the smart gate driver located on a mixed signal integrated circuit and including an analog feedback signal from the load;

the smart gate driver including one or more of an Analog to Digital Converter, a sampling portion of an Analog to Digital Converter, sigma delta modulator, a decoder, and an encoder located on the mixed signal integrated circuit; and

a decoder for decoding a signal, the decoder being located on the primarily digital integrated circuit;

the encoder used to encode the signal, and the signal is used by the converter to regulate the voltage delivered to the load,

wherein the analog feedback signal is encoded using the encoder located on the mixed signal integrated circuit, the encoder comprises an analog to digital converter and a differential encoder connected in series along the control loop.

2. The apparatus of claim 1, wherein the recommended supply voltage of said digital circuit blocks are less than or equal to 3.3 volts.

3. The apparatus of claim 1, wherein the encoder comprises an one or more of an Analog to Digital Converter, a sampling portion of an Analog to Digital Converter, sigma delta modulator and a digital noise resistant encoder connected in series along the control loop.

4. The apparatus of claim 1, further comprising:

a second decoder located on the first integrated circuit;

wherein the encoder comprises the analog to digital converter.

5. The apparatus of claim 4, wherein:

the second decoder receives a control signal from the second integrated circuit, the control signal being used to control the gate driver; and

the control signal contains an embedded synchronization signal.

6. The apparatus of claim 5, wherein the second decoder sends information from the synchronization signal to the analog to digital converter.

7. An apparatus comprising:

a converter for receiving a supply and regulating a load, the converter using a smart gate driver, the smart gate driver including an analog feedback signal from the load, the smart gate driver further including one or more of;

an Analog to Digital Converter, a sampling portion of an Analog to Digital Converter, a sigma delta modulator, an encoder, and a decoder;

a control loop for controlling the converter in response to the analog feedback signal; and

a controller located on the control loop, the controller controlling the smart gate driver via the control loop;

the controller located on a first integrated circuit fabricated using a primarily digital process, and the smart gate driver located on a second integrated circuit fabricated using a mixed signal process

a first encoder on the first integrated circuit for encoding a control signal from the controller;

the smart gate driver including the encoder on the second integrated circuit for encoding a feedback signal; and

a printed circuit board coupled to both the first integrated circuit and the second integrated circuit.

8. The apparatus of claim 7, further comprising:

a second gate driver for regulating the load;

a second control loop for controlling the second gate driver in response to a second feedback signal;

wherein the second control loop and the control loop share a feedback signal routing line; and

wherein the feedback signal and the second feedback signal are encoded to be transmitted serially on the feedback signal routing line.

9. The apparatus of claim 7, further comprising:

a second gate driver for regulating the load;

the smart gate driver including the first sigma delta modulator located on said second integrated circuit;

a second sigma delta modulator located on a third integrated circuit, said third integrated circuit also housing said second gate driver; and

a decimation filter located on said first integrated circuit;

wherein said first sigma delta modulator produces a bit stream representing said feedback signal;

said second sigma delta modulator produces a second bit stream representing said second feedback signal; and

said decimation filter resolves said feedback signal and said second feedback signal.

10. The apparatus of claim 7, wherein:

the feedback signal is encoded using the encoder located on the second integrated circuit; and

the encoder comprises an analog to digital converter and a differential encoder connected in series along the control loop.

11. The apparatus of claim 7, wherein:

the first encoder encodes a set of other control signals from the controller, the set of other control signals being used to control a set of other converters; and

the set of other converters are located on the printed circuit board.

12. The apparatus of claim 7, wherein the second integrated circuit including the smart gate driver includes a plurality of power switches.

13. The apparatus of claim 10, wherein the analog to digital converter is the sigma delta modulator, and the sigma delta modulator applies a noise shaping to the feedback signal.

14. The apparatus of claim 10, further comprising a multiplexer located on the second integrated circuit, the multiplexer being configured to receive multiple load condition signals and pass them to the analog to digital converter.

15. The apparatus of claim 11, wherein the first integrated circuit is located on a periphery of the printed circuit board.

16. The apparatus of claim 12, wherein the second integrated circuit comprises an integrated circuit package, with a plurality of integrated circuits.

17. The apparatus of claim 14, further comprising:

a decimation filter located on the first integrated circuit; and

the sigma delta modulator located on the second integrated circuit serving as the encoder for the feedback signal;

wherein the decimation filter resolves a bit stream from the sigma delta modulator to decode the feedback signal.

18. An apparatus comprising:

a circuit coupled to a supply and a load, the circuit regulating a voltage level applied to the load based on a control signal;

a controller for controlling the circuit based on a feedback signal received from the smart gate driver, the controller generating the control signal; and

a second circuit coupled to the supply and the load, the circuit regulating the voltage level applied to the load based on a second control signal, the second circuit comprising a smart gate driver including an analog feedback signal from the load, the smart gate driver further including one or more of an Analog to Digital Converter, a sampling portion of an Analog to Digital Converter, sigma delta modulator, encoder, and a decoder;

the controller also controls the second circuit, the controller controls the second circuit based on a second feedback signal received from the load, and the controller generates the second control signal based the second feedback signal;

the controller is on a first digital integrated circuit and the circuit and the second circuit are on one or more mixed signal integrated circuits; and

wherein said first feedback signal and said second feedback signal are routed on at least one common circuit trace between said different integrated circuits;

a first encoder on the first integrated circuit for encoding a control signal from the controller;

the smart gate driver including the encoder on the second integrated circuit for encoding a feedback signal; and

a printed circuit board coupled to both the first integrated circuit and the second integrated circuit.

19. The apparatus of claim 18, wherein:

the different integrated circuits are all located on the same printed circuit board; and

said common circuit trace is a single serial bus.

20. The apparatus of claim 18, further comprising:

a delta sigma modulator located on the same integrated circuit as the first circuit;

a second delta sigma modulator located on the same integrated circuit as the second circuit; and

a decimation filter located on the same integrated circuit as the controller;

wherein the delta sigma modulator and the second sigma delta modulator operate out of phase to create serial bit streams that are routed to the decimation filter using the same circuit trace or set of circuit traces.

21. The apparatus of claim 20, further comprising:

a decoder located on the same integrated circuit as the first circuit, the decoder for decoding a converter control signal from the controller;

wherein the decoder passes a synchronization signal to the delta sigma modulator.