Scalable architecture for IP block integration
First Claim
1. An integrated circuit, comprising:
- a plurality of programmable logic blocks;
an intellectual property (IP) circuit block that is adjacent to at least one of the plurality of programmable logic blocks and that comprises a plurality of endpoints;
a local configuration source that is adjacent to the IP circuit block and that is used to address the plurality of endpoints in the IP circuit block; and
a pipeline stage that is coupled to the plurality of endpoints and that routes access commands from the local configuration source to at least one of the plurality of endpoints.
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Accused Products
Abstract
A scalable circuit architecture for programmable circuitry is provided. Intellectual property (IP) blocks may be integrated into a circuit design and may be formed next to programmable logic sectors on which user logic functions are implemented. IP blocks may receive configuration data from sub-system managers (SSMs) that serve as a local configuration source for the IP blocks. Configurable endpoints in the IP blocks may be represented by memory mapped addresses that may be decoded by pipeline decoders having delay elements that prevent read data collision. A reroute layer may serve as an interface between IP blocks and one or more programmable logic sectors. The reroute layer may have a higher number of connections at a logic sector interface compared to the number of connections at an IP block interface. An IP block may route clock signals having different frequencies to respective different rows or regions in the programmable logic sectors.
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Citations
17 Claims
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1. An integrated circuit, comprising:
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a plurality of programmable logic blocks; an intellectual property (IP) circuit block that is adjacent to at least one of the plurality of programmable logic blocks and that comprises a plurality of endpoints; a local configuration source that is adjacent to the IP circuit block and that is used to address the plurality of endpoints in the IP circuit block; and a pipeline stage that is coupled to the plurality of endpoints and that routes access commands from the local configuration source to at least one of the plurality of endpoints. - View Dependent Claims (2, 3, 4, 5, 6)
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7. Programmable circuitry, comprising:
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logic fabric having programmable blocks arranged in rows and columns; an intellectual property (IP) circuit block having multiple endpoints and a clock generator that provides at least one clock signal to the logic fabric; a local configuration source having a configuration clock generator that generates a configuration clock signal for configuring the IP circuit block, wherein the local configuration source addresses the multiple endpoints in the IP circuit block; and a pipeline stage that is coupled to the multiple endpoints and that routes access commands from the local configuration source to at least one of the plurality of endpoints. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. Circuitry, comprising:
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an array of programmable logic blocks; an intellectual property (IP) block having multiple endpoints that is adjacent to the array of logic blocks; a pipelined reroute layer having a first set of connections between a first interface of the reroute layer and the multiple endpoints in the IP block, and further having a second set of connections between a second interface of the reroute layer and the array logic blocks, wherein the first set of connections has a first connection density that is higher than a second connection density of the second set of connections; and a local configuration source that addresses the multiple endpoints in the IP block and that configures the pipelined reroute layer to map a first connection at the first interface to a second connection at the second interface, and wherein the pipelined reroute layer routes signals between the first and second connections. - View Dependent Claims (15, 16, 17)
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Specification