Adaptive multi-service data framing

• US 9,847,945 B2
• Filed: 03/23/2015
• Issued: 12/19/2017
• Est. Priority Date: 12/27/2007
• Status: Expired due to Fees

• Current Assignee: Exalt Wireless Incorporated
• Original Assignee: Exalt Wireless Incorporated
• Inventors: Smidth, Peter
• Primary Examiner(s): Kao, Jutai
• Application Number:
  US14/666,138
• Publication Number:
  US 20150195207A1
• Time in Patent Office: 1,002 Days
• CPC Class Codes: H04L 1/0003 by switching between different modulation schemes
• CPC Class Codes: H04L 1/0017 where the mode-switching is based on Quality of Service requirement
• CPC Class Codes: H04L 12/54 Store-and-forward switching systems packet switching systems H04L45/00, H04L47/00
• CPC Class Codes: H04L 47/24 Traffic characterised by specific attributes, e.g. priority or QoS
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04W 28/04 Error control
• CPC Class Codes: H04W 28/22 Negotiating communication rate
• CPC Class Codes: H04W 72/0446 Resources in time domain, e.g. slots or frames

Abstract

When a signal-to-noise ratio affecting radio communication becomes sufficiently low, then the data transmission rate is responsively decreased in compensation. The signal-to-noise ratio of the communication link is thereby increased. Data for multiple different services is transmitted in data packets between two radios. By allocating one part, or time slot, of the data packet'"'"'s payload to one service, and allocating another part, or time slot, of the data packet'"'"'s payload to another service, communications sessions for multiple services can be maintained concurrently. Services are prioritized relative to each other. In case the signal-to-noise ratio becomes too low, data packet portions that are related to lower-priority services can be omitted from some data packets before those data packets are transmitted. Data remaining in the packet can be sent at a reduced data transmission rate without causing the quality of service for the remaining packets to fall below the minimum required level.

Claims

1. A system comprising:

a plurality of framing buffers in a transmitting device;

wherein a first framing buffer of the plurality of framing buffers comprises a first first-in-first-out (FIFO) mechanism that receives data for a first communication service and a first particular input signal that regulates a rate at which data is read out of the first FIFO mechanism;

wherein a second framing buffer of the plurality of framing buffers comprises a second FIFO mechanism that receives data for a second communication service and a second particular input signal that regulates a rate at which data is read out of the second FIFO mechanism;

an output mechanism in the transmitting device that is configured to insert data from the first framing buffer of the plurality of framing buffers into a first subframe of a first superframe;

a switch connected to the output mechanism in the transmitting device that is configured to cause the output mechanism to alternate between framing buffers of the plurality of framing buffers in order to cause the output mechanism to insert data from the second framing buffer of the plurality of framing buffers into a second subframe of the first superframe;

a subtract mechanism that subtracts a difference from a specified value and produces a desired value;

a clock oscillator that generates a first data clock signal based at least in part on the desired value;

a plurality of de-framing buffers in a receiving device, wherein the plurality of de-framing buffers includes a first de-framing buffer;

wherein the first de-framing buffer further comprises;

a loop filter that receives the desired value from the subtract mechanism, generates a graduated value based on the desired value by gradually changing the graduated value over time, and outputs the graduated value to the clock oscillator;

wherein the clock oscillator generates the first data clock signal based at least in part on the graduated value.

2. The system of claim 1 wherein the switch is further configured to cause the output mechanism to alternate between framing buffers of the plurality of framing buffers at a fixed interval.

3. The system of claim 1 wherein the switch is further configured to cause the output mechanism to alternate between framing buffers of the plurality of framing buffers after the output mechanism has read a subset of the data for the first communication service.

4. The system of claim 1 wherein the first framing buffer further comprises:

a sample and hold mechanism that samples and holds a difference between a read pointer of the first FIFO mechanism and a write pointer of the first FIFO mechanism.

5. The system of claim 1:

wherein the first de-framing buffer of the plurality of de-framing buffers comprises;

a third FIFO mechanism that receives the data for the first communication service and outputs the data for the first communication service at a first read rate that is controlled by the first data clock signal; and

wherein a second de-framing buffer of the plurality of de-framing buffers comprises;

a fourth FIFO mechanism that receives the data for the second communication service and outputs the data for the second communication service at a second read rate that is controlled by a second data clock signal.

6. The system of claim 5, wherein the specified value is received by the first de-framing buffer as input in order to replicate the rate at which data is read out of the first FIFO mechanism.

7. The system of claim 5, further comprising a sample and a hold mechanism, wherein the sample and the hold mechanism samples a difference between a read pointer of the third FIFO mechanism and a write pointer of the third FIFO mechanism at a superframe boundary.

8. A framing buffer device comprising:

a first in first out (FIFO) mechanism that receives (a) data for a communication service and (b) a particular input signal that regulates a rate at which data is read into the FIFO mechanism;

a sample and hold mechanism that samples and holds a difference between a read pointer of the FIFO mechanism and a write pointer of the FIFO mechanism; and

a subtract mechanism that subtracts the difference from a specified value and produces a buffer loading error that is used to generate the particular input signal;

wherein the sample and hold mechanism samples the difference between the read pointer of the FIFO mechanism and the write pointer of the FIFO mechanism at a superframe boundary.

9. The framing buffer device of claim 8, wherein data output from the FIFO mechanism is inserted into a subframe of a first superframe that contains multiple subframes, each of which contains data for a separate communication service.

10. The framing buffer device of claim 9, wherein:

data output from the FIFO mechanism is inserted into a subframe of a second superframe that contains multiple subframes, each of which contains data for a separate communication service;

wherein the second superframe contains a different number of subframes than the first superframe; and

wherein the subframe of the second superframe into which data output from the FIFO mechanism is inserted is a different size than the subframe of the first superframe into which data output from the FIFO mechanism is inserted.

11. The framing buffer device of claim 8, wherein the buffer loading error is used to generate a control word that indicates a length of a variable length subframe of a superframe that contains multiple subframes.

12. The framing buffer device of claim 11, wherein three or more copies of the control word are inserted into the variable length subframe.

13. The framing buffer device of claim 8, wherein the particular input signal decreases the rate at which data is read out of the FIFO mechanism by causing dummy data to be read out of the FIFO mechanism instead of the data for the communication service.

14. The framing buffer device of claim 8, wherein the specified value indicates a desired fullness for the FIFO mechanism.

15. The framing buffer device of claim 8, further comprising a clock oscillator that causes the FIFO mechanism to accept and store the data at a constant rate.

16. A de-framing buffer device comprising:

a first in first out (FIFO) mechanism that receives data for a particular communication service of a plurality of communication services and outputs the data at a read rate that is controlled by a data clock signal;

a sample and hold mechanism that samples and holds a difference between a read pointer of the FIFO mechanism and a write pointer of the FIFO mechanism;

a subtract mechanism that subtracts the difference from a specified value and produces a desired value; and

a clock oscillator that generates the data clock signal based at least in part on the desired value;

a loop filter that receives the desired value from the subtract mechanism, generates a graduated value based on the desired value by gradually changing the graduated value over time, and outputs the graduated value to the clock oscillator;

wherein the clock oscillator generates the data clock signal based at least in part on the graduated value.

17. The de-framing buffer device of claim 16, wherein the data for the particular communication service that is received by the FIFO mechanism was transmitted within a superframe that contains multiple subframes, each of which contains data for a different communication service of a plurality of communication services.

18. The de-framing buffer device of claim 16, wherein the sample and hold mechanism samples the difference between the read pointer of the FIFO mechanism and the write pointer of the FIFO mechanism at a superframe boundary.

19. The de-framing buffer device of claim 16, wherein the specified value relates to a rate at which the data was originally received at a transmitter.