Reset supervisor
First Claim
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1. A device comprising:
- a first processor and a second processor each configured to receive an input signal;
wherein the first processor is configured to process the input signal to generate an output signal and transmit the output signal to the second processor;
wherein the second processor is configured to(i) compare the input signal to the output signal to determine whether the input signal corresponds to the output signal, and(ii) transmit a reset signal to the first processor in response to determining that the input signal does not correspond to the output signal; and
wherein the first processor is further configured to load firmware in response to receiving the reset signal.
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Abstract
Multiple processor systems are provided. A first processor is configured to monitor the state of at least one other processor by comparing received signals. When the first processor determines that another processor needs to be reset, the first processor provides a reset signal to a reset pin of the processor that needs to be reset. The first processor may reset itself after providing the reset signal.
10 Citations
20 Claims
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1. A device comprising:
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a first processor and a second processor each configured to receive an input signal; wherein the first processor is configured to process the input signal to generate an output signal and transmit the output signal to the second processor; wherein the second processor is configured to (i) compare the input signal to the output signal to determine whether the input signal corresponds to the output signal, and (ii) transmit a reset signal to the first processor in response to determining that the input signal does not correspond to the output signal; and wherein the first processor is further configured to load firmware in response to receiving the reset signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A device comprising:
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a first processor and a second processor each configured to receive an input signal; wherein the second processor is configured to transmit, to the first processor, a reset signal in response to determining that the input signal does not correspond to an output signal generated by and received from the first processor which is configured to process the input signal to generate the output signal; and wherein the first processor is further configured to load firmware in response to receipt of the reset signal.
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Specification