Methods for operating a memory array

• US 9,851,913 B2
• Filed: 02/01/2016
• Issued: 12/26/2017
• Est. Priority Date: 12/31/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bedeschi, Ferdinando, Resta, Claudio, Ferraro, Marco
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US15/012,478
• Publication Number:
  US 20160162213A1
• Time in Patent Office: 694 Days
• Field of Search: 365163, 365189011, 36518915, 36518916, 36518909
• CPC Class Codes: G06F 3/0622 in relation to access
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0059 Security or protection circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 13/02 using elements whose operation depends upon chemical change G11C13/0009 takes precedence
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect

Abstract

Methods of operating memory arrays are described. In various embodiments, a method includes determining a pattern to be written to a memory array, the pattern comprising both data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored, and writing the pattern to the memory array. Other methods of operation are also described.

Claims

1. A method of operating a memory array, the method comprising:

determining a pattern to be written to the memory array, the determined pattern comprising both data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored;

writing the determined pattern to the memory array;

providing a write password; and

erasing the determined pattern from the memory array if the write password is incorrect.

2. The method of claim 1, further comprising defining a starting condition for each cell in the memory array prior to storing a plurality of bits in the memory array, the starting condition being defined by providing either one or more hard reset pulses or one or more soft reset pulses to each of the cells in the memory array.

3. The method of claim 2, wherein the one or more hard reset pulses have a first amplitude, and the one or more soft reset pulses have a second amplitude that is different from the first amplitude.

4. The method of claim 2, wherein the one or more hard reset pulses are to allow writing a logical “

0,” and

the one or more soft reset pulses are to allow writing a logical “

1”

to selected ones of the cells in the memory array.

5. The method of claim 1, wherein the memory array comprises plurality of phase-change memory (PCM) cells.

6. The method of claim 1, further comprising executing two or more reset sequences on the memory array prior to writing the determined pattern to the memory array.

7. The method of claim 1, further comprising comparing the write password with information stored in a programmable memory to verify a validity of the write password.

8. The method of claim 1, further comprising writing determined pattern to the memory array using an internal state machine.

9. The method of claim 1, wherein the method is for encrypting the memory array.

10. A method of operating a memory array, the method comprising:

executing a set sequence on the memory array prior to performing the read of the memory array, the set sequence comprising an all-zero pattern target for the memory array, the pattern being a non-all-zero pattern;

performing a read of the memory array to obtain a pattern derived from executing the set sequence, and obtain an additional pattern comprising both real data hits having sensitive information to he stored and data bits having a state that is unimportant to the sensitive information to be stored; and

adjusting an internal read reference to maintain a margin for obtaining the additional pattern.

11. The method of claim 10, further comprising, subsequent to performing the read, executing two or more reset sequences on the memory array to re-hide the derived pattern in the memory array.

12. The method of claim 10, further comprising:

executing a set sequence on the memory array prior to performing the read of the memory array, the set sequence comprisimg a first pattern target for the memory array, the pattern being a second pattern different from the first pattern; and

performing the read of the memory array to obtain a pattern derived from executing the set sequence.

13. The method of claim 12, further comprising, subsequent to performing the read, executing two or more reset sequences on the memory array to re-hide the derived pattern in the memory array.

14. The method of claim 10, wherein the method is for decrypting the memory array.

15. The method of claim 10, further comprising:

issuing a read password prior to performing the read of the memory array; and

comparing the read password with information stored in a programmable memory to verify a validity of the read password.

16. The method of claim 10, further comprising merging the real data bits having sensitive information to be stored and the data bits having a state that is unimportant to the sensitive information to he stored inside logic packets of bits.

17. The method of claim 10, further comprising increasing the internal read reference current to maintain the margin.

18. A tangible computer-readable medium having no transitory signals and containing instructions that, when executed by one or more hardware-based processors of a machine, cause the machine to perform operations comprising:

determining a pattern to be written to the memory array, the determined pattern comprising both data bits having sensitive information to be stored and data hits having a state that is unimportant to the sensitive information to be stored;

writing the determined pattern to the memory array;

providing a write password; and

erasing the determined pattern from the memory array if the write password is incorrect.

19. A tangible computer-readable medium having no transitory signals and containing instructions that, when executed by one or more hardware-based processors of a machine, cause the machine to perform operations comprising:

executing a set sequence on the memory array prior to performing the read of the memory array, the set sequence comprising an all-zero pattern target for the memory array, the pattern being a non-all-zero pattern;

performing a read of the memory array to obtain a pattern derived from executing the set sequence, the pattern comprising both real data bits having sensitive information to be stored and data hits having a state that is unimportant to the sensitive information to he stored; and

adjusting an internal read reference to maintain a margin for obtaining the pattern.

20. A method of operating a memory array, the method comprising:

executing a set sequence on the memory array prior to performing the read of the memory array, the set sequence comprising a first pattern target for the memory array, the pattern being a second pattern different from the first pattern;

performing a read of the memory array to obtain a pattern derived from executing the set sequence and obtain an additional pattern comprising both real data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored; and

adjusting an internal read reference to maintain a margin for obtaining the additional pattern.

21. A tangible computer-readable medium having no transitory signals and containing instructions that, when executed by one or more hardware-based processors of a machine, cause the machine to perform operations comprising:

executing a set sequence on the memory array prior to performing the read of the memory array, the set sequence comprising a first pattern target for the memory array, the pattern being a second pattern different from the first pattern;

performing a read of the memory array to obtain a pattern derived from executing the set sequence and obtain an additional pattern comprising both real data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored; and

adjusting an internal read reference to maintain a margin for obtaining the additional pattern.