Flash memory chip processing

• US 9,851,921 B1
• Filed: 10/21/2015
• Issued: 12/26/2017
• Est. Priority Date: 07/05/2015
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Weingarten, Hanan, Sabbag, Erez
• Primary Examiner(s): Farrokh, Hashem
• Application Number:
  US14/919,558
• Time in Patent Office: 797 Days
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence

Abstract

According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to sample a flash memory cell that belongs to a die, by attempting, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value; sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples; defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell; and determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample. The processor may belong to the sampling circuit or may not belong to the sampling circuit.

Claims

1. A method for sampling a flash memory cell that belongs to a die, the method comprising:

attempting, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value;

sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples;

defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell;

determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample; and

determining an allocation of the flash memory cell based upon the reliability of the data sample.

2. The method according to claim 1 wherein the determining of the reliability comprises searching for a difference between the multiple samples.

3. The method according to claim 1 wherein the determining of the reliability comprises assigning a reliability score that is responsive to an order, within the multiple samples, of a first sample that differs from a preceding sample.

4. The method according to claim 3 comprising assigning a reliability score that represent a decrease in reliability with an increase in the order of the first sample.

5. The method according to claim 1 wherein the determining of the reliability comprises assigning a first reliability score when all the samples have a same value;

and assigning a second reliability score when one of the multiple samples differs from another sample;

wherein the second reliability score is indicative of a lower reliability than the first reliability score.

6. The method according to claim 1 further comprising outputting, to a flash memory controller located outside the die, information about the reliability of the data sample.

7. The method according to claim 1, comprising decoding, by the processor, the data sample;

wherein the decoding comprises utilizing information, generated by the processor, related to the reliability of the data sample.

8. The method according to claim 1, comprising receiving, by the processor error correction information that was generated outside the die and relates to the data sample;

and decoding, by the processor, the data sample;

wherein the decoding comprises (a) utilizing information, generated by the processor, related to the reliability of the data sample and (b) utilizing the error correction information.

9. The method according to claim 1, comprising controlling an execution of operations applied on the data sample in response to the reliability of the data sample.

10. The method according to claim 1, comprising preventing a copyback operation when the reliability of the data sample is below a reliability threshold.

11. The method according to claim 1, comprising selecting between an execution of a copyback operation and a provision of the data sample to an external flash memory controller based upon the reliability of the data sample.

12. A non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to sample a flash memory cell that belongs to a die, by:

attempting, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value;

sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples;

defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell;

determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample; and

preventing a copyback operation when the reliability of the data sample is below a reliability threshold.

13. The non-transitory computer readable medium of claim 12, wherein an allocation of the flash memory cell is determined based upon the reliability of the data sample.

14. The non-transitory computer readable medium of claim 12, wherein the determining of the reliability comprises searching for a difference between the multiple samples.

15. A semiconductor die that comprises a processor, a sampling circuit and a flash memory array;

wherein the sampling circuit is configured to;

(a) attempt, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value;

(b) sample an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples;

wherein the processor is configured to define a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell;

(c) determine a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample; and

(d) select between an execution of a copyback operation and a provision of the data sample to an external flash memory controller based upon the reliability of the data sample.

16. The semiconductor die of claim 15, wherein the sampling circuit is further configured to prevent a copyback operation when the reliability of the data sample is below a reliability threshold.

17. The semiconductor die of claim 15, wherein the sampling circuit is further configured to determine an allocation of the flash memory cell based upon the reliability of the data sample.

18. A method for sampling a flash memory cell that belongs to a die, the method comprising:

performing a first attempt, during a first gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value;

sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the first voltage gate change period to provide multiple first samples; and

defining a first given sample of the first multiple samples as a first data sample that represents data stored in the flash memory cell;

determining, by a processor that belongs to the die, a reliability of the first data sample based on one or more samples of the first multiple samples that differ from the first given sample;

performing a second attempt, during a second gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first intermediate value to a third value;

wherein the second attempt starts before a completion of the first attempt and when the gate voltage of the flash memory cell reached the first intermediate value;

defining a second given sample of the second multiple samples as a second data sample that represents the data stored in the flash memory cell;

determining, by the processor, a reliability of the second data sample based on one or more samples of the second multiple samples that differ from the second given sample; and

preventing a copyback operation when the reliability of the first data sample or the second data sample is below a reliability threshold.

19. The method of claim 18, further comprising determining an allocation of the flash memory cell based upon the reliability of the first data sample or the second data sample.

20. The method of claim 18, further comprising selecting between an execution of a copyback operation and a provision of the second data sample to an external flash memory controller based upon the reliability of the second data sample.