Apparatus and method for read time control in ECC-enabled flash memory

• US 9,852,024 B2
• Filed: 04/19/2016
• Issued: 12/26/2017
• Est. Priority Date: 04/19/2016
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Huang, Koying
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US15/132,771
• Publication Number:
  US 20170300378A1
• Time in Patent Office: 616 Days
• Field of Search: 714764, 714763, 714770, 714773
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2207/2281 Timing of a read operation
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

In a flash semiconductor memory, sense and contiguous ECC coding operations are carried out over a range of V_CC values without wasted time by allocating a predetermined number of clocks to the combined operations rather than to the individual operations and operating at higher frequency for high V_CC values, and lower frequency for low V_CC values.

Claims

1. A semiconductor memory comprising:

a flash memory array;

a plurality of sense amplifiers coupled to the flash memory array;

a plurality of fast memory elements coupled to the plurality of sense amplifiers;

an error correction code (“

ECC”

) circuit coupled to the fast memory elements;

at least one dummy flash memory cell associated with the flash memory array;

at least one dummy sense amplifier coupled to the dummy flash memory cell;

a driver having an input coupled to the dummy sense amplifier and an output coupled to the fast memory elements; and

a memory controller coupled to the flash memory array, the sense amplifiers, the dummy sense amplifier, and the ECC circuit, and comprising logic and memory elements for executing the functions of;

at nominal supply voltage (“

V_CC”

) and at a first frequency, performing a sense operation and a contiguous ECC operation over a predetermined total number of clock pulses, and over respective numbers of clock pulses having a first ratio relationship;

at high V_CC and at a second frequency greater than the first frequency, performing the sense operation and the contiguous ECC operation over the predetermined total number of clock pulses, and over respective numbers of clock pulses having a second ratio relationship smaller than the first ratio relationship; and

at low V_CC and at a third frequency less than the first frequency, performing the sense operation and the contiguous ECC operation over the predetermined total number of clock pulses, and over respective numbers of clock pulses having a third ratio relationship greater than the first ratio relationship.

2. The semiconductor memory of claim 1 wherein the flash memory array comprises a NOR flash memory array.

3. The semiconductor memory of claim 1 wherein the flash memory array comprises a NAND flash memory array.

4. The semiconductor memory of claim 1 wherein the predetermined total number of clock pulses is 9, the first ratio relationship is 3.5, the second ratio relationship is 1.0, and the third ratio relationship is 4.2.

5. The semiconductor memory of claim 1 further comprising

an additional dummy flash memory cell associated with the flash memory array, the dummy flash memory cell being a read-zero cell and the additional dummy flash memory cell being a read-one cell;

and

an additional sense amplifier coupled to the additional dummy flash memory cell;

wherein the driver has an additional input coupled to the additional dummy sense amplifier.

6. The semiconductor memory of claim 5 wherein the driver comprises a logic circuit responsive to inputs from the sense amplifier and the additional sense amplifier to generate a latch control pulse.

8. The semiconductor memory of claim 1 wherein the flash memory array comprises a NOR flash memory array.

9. The semiconductor memory of claim 1 wherein the flash memory array comprises a NAND flash memory array.

7. A semiconductor memory comprising:

a flash memory array;

a plurality of sense amplifiers coupled to the flash memory array;

a plurality of fast memory elements coupled to the plurality of sense amplifiers;

an error correction code (“

ECC”

) circuit coupled to the fast memory elements;

a dummy read-zero flash memory cell associated with the flash memory array;

a first dummy sense amplifier coupled to the read-zero dummy flash memory cell;

a dummy read-one flash memory cell associated with the flash memory array;

a second dummy sense amplifier coupled to the read-one dummy flash memory cell;

a logic circuit having a first input coupled to the first dummy sense amplifier and a second input coupled to the second dummy sense amplifier to provide at an output thereof a latch control pulse as a function of differences in sense time of the first dummy sense amplifier and the second dummy sense amplifier, the output of the logic circuit being coupled to the fast memory elements; and

a memory controller coupled to the flash memory array, the sense amplifiers, the dummy sense amplifier, and the ECC circuit, and comprising logic and memory elements for executing the functions of;

at nominal supply voltage (“

V_CC”

) and at a first frequency, performing a sense operation and a contiguous ECC operation over a predetermined total number of clock pulses, and over respective numbers of clock pulses having a first ratio relationship;

at high V_CC and at a second frequency greater than the first frequency, performing the sense operation and the contiguous ECC operation over the predetermined total number of clock pulses, and over respective numbers of clock pulses having a second ratio relationship smaller than the first ratio relationship; and

at low V_CC and at a third frequency less than the first frequency, performing the sense operation and the contiguous ECC operation over the predetermined total number of clock pulses, and over respective numbers of clock pulses having a third ratio relationship greater than the first ratio relationship.

10. A method of performing an error correction code (“

ECC”

) processed read of a flash memory array of a semiconductor memory, comprising;

at nominal supply voltage (“

V_CC”

), operating the semiconductor memory at a first frequency, wherein a sense operation and a contiguous ECC operation occur over a predetermined total number of clock pulses, and over respective numbers of clock pulses having a first ratio relationship;

at high V_CC, operating the semiconductor memory at a second frequency greater than the first frequency, wherein the sense operation and the contiguous ECC operation occur over the predetermined total number of clock pulses, and over respective numbers of clock pulses having a second ratio relationship smaller than the first ratio relationship; and

at low V_CC, operating the semiconductor memory at a third frequency less than the first frequency, wherein the sense operation and the contiguous ECC operation occur over the predetermined total number of clock pulses, and over respective numbers of clock pulses having a third ratio relationship greater than the first ratio relationship.

11. The method of claim 10 wherein the flash memory array comprises a NOR flash memory array.

12. The method of claim 10 wherein the flash memory array comprises a NAND flash memory array.