×

Phase locked loop (PLL) timing device evaluation system and method for evaluating PLL timing devices

  • US 9,852,039 B1
  • Filed: 02/03/2016
  • Issued: 12/26/2017
  • Est. Priority Date: 02/03/2016
  • Status: Active Grant
First Claim
Patent Images

1. A method for evaluating Phase Locked Loop (PLL) timing devices comprising:

  • providing an evaluation board including a PLL-timed physical device, an input and output circuit, connector receptacles and control logic;

    providing PLL cards configured to be inserted into at least two of the connector receptacles, each of the PLL cards including a PLL timing device;

    providing one or more backplane emulator card configured to be inserted into one of the connector receptacles, the backplane emulator card having electrical characteristics emulating a portion of a communication system extending between phase locked loop timing devices of the communication system; and

    wherein different PLL cards and different backplane emulator cards can be coupled to the connector receptacles to emulate different configurations of the communication system.

View all claims
  • 3 Assignments
Timeline View
Assignment View
    ×
    ×