×

Method, apparatus and instructions for parallel data conversions

  • US 9,852,109 B2
  • Filed: 12/28/2016
  • Issued: 12/26/2017
  • Est. Priority Date: 09/08/2003
  • Status: Active Grant
First Claim
Patent Images

1. A system comprising:

  • at least one reduced instruction set computer (RISC) processor;

    a system memory to store instructions to be processed by the RISC processor;

    a memory controller to couple the RISC processor to the system memory over a system memory bus; and

    a network interface to couple the RISC processor to a network;

    the RISC processor comprising;

    a register file, within the RISC processor, including a first packed data register and a second packed data register;

    a register renamer within the RISC processor;

    a decoder, within the RISC processor, to decode the instructions, the instructions to include a first instruction;

    a scheduler, within the RISC processor, to queue operations that correspond to the instructions for execution; and

    execution logic, within the RISC processor, coupled to the decoder, the register renamer, and the scheduler, the execution logic to perform out-of-order execution of at least some of the instructions;

    wherein, responsive to a decode of the first instruction by the decoder, the execution logic is to convert a first plurality of packed signed data elements to be stored in the first packed data register to a second plurality of packed unsigned data elements in the second packed data register, one or more of the second plurality of packed unsigned data elements to be saturated;

    the first plurality of packed signed data elements to include floating point data elements and the second plurality of packed unsigned data elements to include integer data elements;

    at least one of the first plurality of packed signed data elements to have a first number of bits, at least one of the second plurality of packed unsigned data elements to have a second number of bits, wherein the second number of bits is one half the first number of bits.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×