Method, apparatus and instructions for parallel data conversions
First Claim
Patent Images
1. A system comprising:
- at least one reduced instruction set computer (RISC) processor;
a system memory to store instructions to be processed by the RISC processor;
a memory controller to couple the RISC processor to the system memory over a system memory bus; and
a network interface to couple the RISC processor to a network;
the RISC processor comprising;
a register file, within the RISC processor, including a first packed data register and a second packed data register;
a register renamer within the RISC processor;
a decoder, within the RISC processor, to decode the instructions, the instructions to include a first instruction;
a scheduler, within the RISC processor, to queue operations that correspond to the instructions for execution; and
execution logic, within the RISC processor, coupled to the decoder, the register renamer, and the scheduler, the execution logic to perform out-of-order execution of at least some of the instructions;
wherein, responsive to a decode of the first instruction by the decoder, the execution logic is to convert a first plurality of packed signed data elements to be stored in the first packed data register to a second plurality of packed unsigned data elements in the second packed data register, one or more of the second plurality of packed unsigned data elements to be saturated;
the first plurality of packed signed data elements to include floating point data elements and the second plurality of packed unsigned data elements to include integer data elements;
at least one of the first plurality of packed signed data elements to have a first number of bits, at least one of the second plurality of packed unsigned data elements to have a second number of bits, wherein the second number of bits is one half the first number of bits.
0 Assignments
0 Petitions
Accused Products
Abstract
Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.
17 Citations
6 Claims
-
1. A system comprising:
-
at least one reduced instruction set computer (RISC) processor; a system memory to store instructions to be processed by the RISC processor; a memory controller to couple the RISC processor to the system memory over a system memory bus; and a network interface to couple the RISC processor to a network; the RISC processor comprising; a register file, within the RISC processor, including a first packed data register and a second packed data register; a register renamer within the RISC processor; a decoder, within the RISC processor, to decode the instructions, the instructions to include a first instruction; a scheduler, within the RISC processor, to queue operations that correspond to the instructions for execution; and execution logic, within the RISC processor, coupled to the decoder, the register renamer, and the scheduler, the execution logic to perform out-of-order execution of at least some of the instructions; wherein, responsive to a decode of the first instruction by the decoder, the execution logic is to convert a first plurality of packed signed data elements to be stored in the first packed data register to a second plurality of packed unsigned data elements in the second packed data register, one or more of the second plurality of packed unsigned data elements to be saturated; the first plurality of packed signed data elements to include floating point data elements and the second plurality of packed unsigned data elements to include integer data elements; at least one of the first plurality of packed signed data elements to have a first number of bits, at least one of the second plurality of packed unsigned data elements to have a second number of bits, wherein the second number of bits is one half the first number of bits. - View Dependent Claims (2, 3)
-
-
4. A system comprising:
-
at least one reduced instruction set computer (RISC) processor; a system memory to store instructions to be processed by the RISC processor; a memory controller to couple the RISC processor to the system memory over a system memory bus; and a network interface to couple the RISC processor to a network; the RISC processor comprising; a register file, within the RISC processor, including a first packed data register and a second packed data register; a register renamer within the RISC processor; a decoder, within the RISC processor, to decode the instructions, the instructions to include a first instruction; a scheduler, within the RISC processor, to queue operations that correspond to the instructions for execution; and an execution unit, coupled to the decoder, the register renamer, and the scheduler, the execution unit to perform out-of-order execution of at least some of the instructions; wherein, responsive to a decode of the first instruction by the decoder, the execution unit is to convert a first plurality of packed signed data elements to be stored in the first packed data register to a second plurality of packed unsigned data elements in the second packed data register, one or more of the second plurality of packed unsigned data elements to be saturated; the first plurality of packed signed data elements to be floating point data elements and the second plurality of packed unsigned data elements to be integer data elements; each of the first plurality of packed signed data elements to have a first number of bits, each of the second plurality of packed unsigned data elements to have a second number of bits, wherein the second number of bits is one half the first number of bits. - View Dependent Claims (5, 6)
-
Specification