Modified design rules to improve device performance

• US 9,852,249 B2
• Filed: 07/24/2013
• Issued: 12/26/2017
• Est. Priority Date: 09/10/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lum, Annie, Tao, Derek C., Lee, Cheng Hung, Lu, Chung-Ji, Cheng, Hong-Chen, Agrawal, Vineet Kumar, Kim, Keun-Young, Cho, Pyong Yun
• Primary Examiner(s): Alam, Mohammed
• Application Number:
  US13/949,683
• Publication Number:
  US 20130311964A1
• Time in Patent Office: 1,616 Days
• Field of Search: 716119
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.

Claims

1. A method of designing a layout of devices, comprising:

designing a layout of gate structures and diffusion regions for a semiconductor device;

identifying a first device having a first gate structure and an irregular diffusion region adjacent to a second device having a second gate structure and a diffusion region different from the irregular diffusion region;

inserting a dummy device between the first gate structure and the second gate structure, wherein the diffusion region shared by the dummy device and the second gate structure is a regular diffusion region, and the regular diffusion region has a rectangular shape and the irregular diffusion region has a non-rectangular shape resulting in a modified layout; and

fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of an inchoate semiconductor integrated circuit.

2. The method of claim 1, further comprising deactivating the dummy device.

3. The method of claim 1, further comprising:

extending the irregular diffusion region of the first gate structure to the dummy device; and

extending the regular diffusion region of the second gate structure to the dummy device.

4. The method of claim 1, further comprising:

extending the irregular diffusion region of the first gate structure to a first side of the dummy device; and

adding an additional diffusion region between the regular diffusion region of the second gate structure and a second side of the dummy device, wherein the additional diffusion region adjacent to the second side of the dummy device is different from the irregular diffusion region adjacent to the first side of the dummy device.

5. The method of claim 1, further comprising:

extending the regular diffusion region of the second gate structure to a first side of the dummy device; and

adding an additional diffusion region having the irregular diffusion region between the first gate structure and a second side of the dummy device, wherein the additional diffusion region adjacent to the first side of the dummy device is different from the irregular diffusion region adjacent to the second side of the dummy device.

6. The method of claim 1, further comprising:

extending the irregular diffusion region of the first gate structure to a first side of the dummy device; and

adding an additional diffusion region between the regular diffusion region of the second gate structure and a second side of the dummy device, wherein the additional diffusion region adjacent to the second side of the dummy device is the same as the irregular diffusion region adjacent to the first side of the dummy device.

7. The method of claim 2, wherein the deactivating includes:

electrically connecting a gate structure of the dummy device to a first reference voltage or a second reference voltage.

8. The method of claim 1, wherein:

the irregular diffusion region of the first device has an L shape.

9. A method of designing a layout of devices, comprising:

designing a layout of gate structures and diffusion regions for a semiconductor device;

identifying a first device having a first gate structure and an irregular diffusion region adjacent to a second device having a second gate structure and a diffusion region different from the irregular diffusion region;

inserting a dummy device between the first gate structure and the second gate structure, wherein the diffusion region shared by the dummy device and the second gate structure is a regular diffusion region, and the regular diffusion region has a rectangular shape and the irregular diffusion region has a non-rectangular shape;

extending the irregular diffusion region of the first gate structure to the dummy device;

extending the regular diffusion region of the second gate structure to the dummy device resulting in a modified layout; and

fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of an inchoate semiconductor integrated circuit.

10. The method of claim 9, further comprising deactivating the dummy device.

11. The method of claim 10, wherein the deactivating includes:

electrically connecting a gate structure of the dummy device to a first reference voltage or a second reference voltage.

12. The method of claim 9, wherein:

the extending the irregular diffusion region of the first gate structure to the dummy device extends the irregular diffusion region to a first side of the dummy device;

and the method further comprises;

adding an additional diffusion region between the regular diffusion region of the second gate structure and a second side of the dummy device, wherein the additional diffusion region adjacent to the second side of the dummy device is different from the irregular diffusion region adjacent to the first side of the dummy device.

13. The method of claim 9, wherein:

the extending the regular diffusion region of the second gate structure to the dummy device extends the regular diffusion region to a first side of the dummy device; and

the method further comprises;

adding an additional diffusion region having the irregular diffusion region between the first gate structure and a second side of the dummy device, wherein the additional diffusion region adjacent to the first side of the dummy device is different from the irregular diffusion region adjacent to the second side of the dummy device.

14. The method of claim 9, wherein:

the extending the irregular diffusion region of the first gate structure to the dummy device extends the irregular diffusion region to a first side of the dummy device; and

the method further comprises;

adding an additional diffusion region between the regular diffusion region of the second gate structure and a second side of the dummy device, wherein the additional diffusion region adjacent to the second side of the dummy device is the same as the irregular diffusion region adjacent to the first side of the dummy device.

15. The method of claim 9, wherein:

the irregular diffusion region of the first device has an L shape.

16. A method of designing a layout of devices, comprising:

designing a layout of gate structures and diffusion regions for a semiconductor device;

identifying a first device having a first gate structure and an irregular diffusion region adjacent to a second device having a second gate structure and a diffusion region different from the irregular diffusion region;

inserting a dummy device between the first gate structure and the second gate structure, wherein the diffusion region shared by the dummy device and the second gate structure is a regular diffusion region, and the regular diffusion region has a rectangular shape and the irregular diffusion region has a non-rectangular shape;

selecting one of the irregular diffusion region of the first gate structure or the regular diffusion region of the second gate structure as an extension-candidate for extension and thereby correspondingly selecting the other of the irregular diffusion region of the first gate structure or the regular diffusion region of the second gate structure as an addition-candidate for addition;

extending the extension-candidate to a first side of the dummy device;

adding an additional diffusion region between the addition-candidate and a second side of the dummy device resulting in a modified layout; and

fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of an inchoate semiconductor integrated circuit.

17. The method of claim 16, further comprising deactivating the dummy device.

18. The method of claim 16, wherein:

the extension-candidate is the irregular diffusion region of the first gate structure;

the addition-candidate is the regular diffusion region of the second gate structure;

the extending the extension-candidate includes;

extending the irregular diffusion region of the first gate structure to the first side of the dummy device; and

the adding the additional diffusion region between the addition-candidate and the second side of the dummy device includes;

adding the additional diffusion region between the regular diffusion region of the second gate structure and the second side of the dummy device, wherein the additional diffusion region adjacent to the second side of the dummy device is different from the irregular diffusion region adjacent to the first side of the dummy device.

19. The method of claim 16, wherein:

the extension-candidate is the regular diffusion region of the second gate structure;

the addition-candidate is the irregular diffusion region of the first gate structure;

the extending the extension-candidate includes;

extending the regular diffusion region of the second gate structure to the first side of the dummy device; and

the adding the additional diffusion region between the addition-candidate and the second side of the dummy device includes;

adding the additional diffusion region having the irregular diffusion region between the first gate structure and the second side of the dummy device, wherein the additional diffusion region adjacent to the first side of the dummy device is different from the irregular diffusion region adjacent to the second side of the dummy device.

20. The method of claim 16, wherein:

the extension-candidate is the regular diffusion region of the second gate structure;

the addition-candidate is the irregular diffusion region of the first gate structure;

the extending the extension-candidate includes;

extending the irregular diffusion region of the first gate structure to the first side of the dummy device; and

the adding the additional diffusion region between the addition-candidate and the second side of the dummy device includes;

adding the additional diffusion region between the regular diffusion region of the second gate structure and the second side of the dummy device, wherein the additional diffusion region adjacent to the second side of the dummy device is the same as the irregular diffusion region adjacent to the first side of the dummy device.