Organic light emitting diode display capable of extending sensing time and reducing an update cycle

• US 9,852,695 B2
• Filed: 11/25/2014
• Issued: 12/26/2017
• Est. Priority Date: 12/16/2013
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Choi, Kyoungsik
• Primary Examiner(s): Karimi, Pegeman
• Application Number:
  US14/552,869
• Publication Number:
  US 20150170578A1
• Time in Patent Office: 1,127 Days
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes

Abstract

An organic light emitting diode display includes a data driving circuit which converts pixel data into a data voltage and supplies the data voltage to data lines during a data enable period, and senses changes in driving characteristics of a display panel within an extended vertical blank period, a scan driving circuit which supplies a scan pulse synchronized with the data voltage to scan lines during the data enable period, and outputs a scan pulse within the extended vertical blank period, and a timing controller which compensates for data of an input image using a compensation value determined based on the changes in the driving characteristics, transmits the compensated data to the data driving circuit, and controls operation timing of the data driving circuit and operation timing of the scan driving circuit.

Claims

1. An organic light emitting diode display, in which one frame period is divided into a data enable period and a vertical blank period, comprising:

a data driving circuit configured to convert pixel data into a data voltage and supply the data voltage to data lines of a display panel during the data enable period, and to sense changes in driving characteristics of the display panel within an extended vertical blank period;

a scan driving circuit configured to supply a scan pulse synchronized with the data voltage to scan lines of the display panel during the data enable period, and to output a scan pulse for sensing the changes in the driving characteristics within the extended vertical blank period; and

a timing controller configured to compensate for data of an input image using a compensation value determined based on the changes in the driving characteristics, transmit the compensated data to the data driving circuit, and control operation timing of the data driving circuit and operation timing of the scan driving circuit,

wherein the timing controller shortens the data enable period defined by an input timing signal and extends the extended vertical blank period to be longer than the vertical blank period defined by the input timing signal, and

wherein the scan driving circuit sequentially outputs n scan pulses to a same line of the display panel within the extended vertical blank period so that the data driving circuit sequentially senses changes in driving characteristics for sub-pixels of n colors included in the same line of the display panel within the extended vertical blank period of the one frame period, where n is a positive integer equal to or greater than 2 and equal to or less than 4.

2. The organic light emitting diode display of claim 1, wherein the timing controller includes:

a first and a second input line memories configured to alternately operate on a per line of the display panel basis and alternately read and write pixel data of one line;

a first and a second frame memories configured to alternately operate on a per frame period of the display panel basis and read and write data input from the first and the second input line memories; and

a memory controller configured to control a read frequency of each of the first and second input line memories to be higher than a write frequency of each of the first and the second input line memories and control read and write operation timing of the first and the second input line memories and read and write operation timing of the first and second frame memories.

3. The organic light emitting diode display of claim 2, wherein the timing controller further includes first and second output line memories configured to alternately operate on a per line of the display panel basis and alternately read and write pixel data input from the first and second frame memories,

wherein the memory controller controls a read frequency and a write frequency of each of the first and second output line memories at the same frequency as the write frequency of the first and second input line memories.

4. The organic light emitting diode display of claim 1, wherein a width of the n scan pulses generated within the extended vertical blank period is greater than a width of the scan pulse generated within the data enable period.

5. The organic light emitting diode display of claim 1, wherein the compensation value includes at least one of an offset value for compensating for changes in a threshold voltage of a driving thin film transistor (TFT) included in each pixel of the display panel and a gain value for compensating for changes in a mobility of the driving TFT.