Nonvolatile semiconductor memory device

• US 9,852,797 B2
• Filed: 07/13/2017
• Issued: 12/26/2017
• Est. Priority Date: 11/29/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Maeda, Takashi
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/648,530
• Publication Number:
  US 20170309337A1
• Time in Patent Office: 166 Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Claims

1. A method of controlling a memory device,

the memory device comprising a plurality of memory strings including first to fourth memory strings, the first memory string including a plurality of memory cells electrically connected in series between a first selection transistor and a second selection transistor, the memory cells including a first memory cell and a second memory cell, the first memory string further including a first transistor provided between the first selection transistor and the first memory cell, a second transistor provided between the first memory cell and the second memory cell, and a third transistor provided between the second memory cell and the second selection transistor, a gate of the first selection transistor in the first memory string being coupled to a gate of a first selection transistor in the second memory string, a gate of a first selection transistor in the third memory string being coupled to a gate of a first selection transistor in the fourth memory string, gates of memory cells in the first to third memory strings being coupled to a gate of a memory cell in the fourth memory string,

the method comprising selectively erasing data stored in either a first group including the first and second memory strings or the second group including the third and fourth memory strings.

2. The method of controlling the memory device according to claim 1, the memory device further comprising:

a first word line coupled to the gates of memory cells in the first to fourth memory strings,

a first line coupled to gates of the first selection transistors in the first and second memory strings; and

a second line coupled to gates of the first selection transistors in the third and fourth memory strings.

3. The method of controlling the memory device according to claim 2, the memory device further comprising

a row decoder including a fourth transistor, a fifth transistor, and a sixth transistor, the sixth transistor being coupled to the first word line, a gate of the fourth transistor being configured to receive a first signal, a gate of the fifth transistor being configured to receive a second signal which is different from the first signal.

4. The method of controlling the memory device according to claim 3, wherein the row decoder includes a block decoder, the block decoder being configured to output the first and second signals.

5. The method of controlling the memory device according to claim 4, wherein the first memory cell and the second memory cell in the first memory string are disposed on the same level from a semiconductor substrate.

6. A method of controlling a memory device,

the memory device comprising:

a plurality of memory strings including first to fourth memory strings, the first memory string including a plurality of memory cells electrically connected in series between a first selection transistor and a second selection transistor, the memory cells including a first memory cell and a second memory cell, the first memory string further including a first transistor provided between the first selection transistor and the first memory cell, a second transistor provided between the first memory cell and the second memory cell, and a third transistor provided between the second memory cell and the second selection transistor, a gate of the first selection transistor in the first memory string being coupled to a gate of a first selection transistor in the second memory string, a gate of a first selection transistor in the third memory string being coupled to a gate of a first selection transistor in the fourth memory string, gates of memory cells in the first to third memory strings being coupled to a gate of a memory cell in the fourth memory string; and

a controller, and

the method comprising an erase operation for only either a first group including the first and second memory strings or a second group including the third and fourth memory strings by the controller.

7. The method of controlling the memory device according to claim 6, the memory device further comprising:

a first word line coupled to the gates of memory cells in the first to fourth memory strings;

a first line coupled to gates of the first selection transistors in the first and second memory strings; and

a second line coupled to gates of the first selection transistors in the third and fourth memory strings.

8. The method of controlling the memory device according to claim 7, the memory device further comprising:

a row decoder including a fourth transistor, a fifth transistor, and a sixth transistor, the sixth transistor being coupled to the first word line, a gate of the fourth transistor being configured to receive a first signal, a gate of the fifth transistor being configured to receive a second signal which is different from the first signal.

9. The method of controlling the memory device according to claim 8, wherein the row decoder includes a block decoder, the block decoder being configured to output the first and second signals.

10. The method of controlling the memory device according to claim 9, wherein the first memory cell and the second memory cell in the first memory string are disposed on the same level from a semiconductor substrate.