System for generating a test pattern to detect and isolate stuck faults for an interface using transition coding

• US 9,852,806 B2
• Filed: 06/22/2015
• Issued: 12/26/2017
• Est. Priority Date: 06/20/2014
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Stauffer, David R., Stewart, Andrew Kevin John, Keay, John D.
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US14/746,477
• Publication Number:
  US 20150370676A1
• Time in Patent Office: 918 Days
• CPC Class Codes: G11C 2029/1802 Address decoder
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/18 Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
• CPC Class Codes: G11C 29/702 by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

Conventional methods using signal test patterns to identify wiring errors are difficult to apply to interfaces encoding information as signal state transitions rather than directly as signal states. A system utilizing excitation of wires with selected transition coded patterns and evaluation of received results is described to identify failed wire connections. This approach may be advantageously used to provide fault detection and redundant path selection in systems incorporating stacked chip interconnections using Through Silicon Vias.

Claims

1. A system comprising:

a decoder configured to decode a sequence of received transition codewords of a transition code into a plurality of sets of m data bits, each codeword having n elements and corresponding to one set of m data bits, the received transition codewords corresponding to valid transition codewords having been transmitted via n wires of an egress path having a spare wire in addition to the n wires, each valid transition codeword and having c transitions, and wherein any set of c−

1 transitions of the c transitions corresponds to a valid reduced-transition codeword, wherein n and c, and m are integers greater than or equal to 2; and

,

a data loopback circuit configured to;

receive the plurality of sets of m data bits;

detect two or more sets of m data bits as corresponding to valid reduced-transition codewords indicative of an egress wire fault, the valid reduced-transition codewords collectively forming a group of valid reduced-transition codewords associated with one of the n wires of the egress path associated with the egress wire fault; and

generate a plurality of sets of m response bits comprising (i) the detected two or more sets of m data bits and (ii) at least one set of m response bits corresponding to an egress fault indication codeword; and

an encoder configured to encode the plurality of sets of m response bits into a plurality of response codewords having n elements and to responsively transmit the response codewords via n wires of an ingress path.

2. The system of claim 1, wherein the egress-fault indication codeword is a transition codeword having TC number of transitions, wherein TC is an integer according to:

c<

TC or TC<

c−

1.

14. The system of claim 1, further comprising a steering logic circuit connected to the egress path configured to reroute codeword elements from the wire associated with the egress wire fault to the spare wire of the egress path.

15. The system of claim 14, wherein the steering logic circuit comprises a plurality of multiplexers, each multiplexor connected to two wires of the egress path and configured to receive a selection control signal.

16. The system of claim 14, wherein the steering logic circuit is configured to receive control signals from a system management interface.

3. A system comprising:

a pattern generator configured to generate a plurality of sets of m data bits representing a sequence of valid transition codewords of a transition code, each valid transition codeword comprising n elements and having c transitions, wherein any set of c−

1 transitions of the c transitions corresponds to a valid reduced-transition codeword, and wherein m, n, and c, are integers greater than or equal to 2;

an encoder configured to generate the sequence of valid transition codewords based on the plurality of sets of m data bits and to transmit the sequence of codewords on n wires of an egress path, the egress path further comprising a spare wire in addition to the n wires;

a decoder configured to receive a sequence of response codewords via n wires of an ingress path further comprising a spare wire in addition to the n wires, the decoder configured to decode the sequence of response codewords into a plurality of sets of m response bits;

a pattern checker configured to receive the plurality of sets of m response bits and to generate a listing of received reduced-transition codewords, and to responsively determine (i) a wire index of a wire fault based on the listing of received reduced-transition codewords and (ii) a path associated with the wire fault based on the presence of an egress fault indication codeword, the pattern checker configured to responsively generate a set of wire steering control signals; and

wire steering circuits connected to the egress and ingress paths, wherein one of the steering circuits is configured to reroute codeword elements from the wire on the determined path having the wire index to the spare wire of the determined path.

4. The system of claim 3, wherein the listing corresponds to a combination of states of state elements.

5. The system of claim 4, wherein the state elements are flip-flops.

6. The system of claim 4, wherein the pattern checker comprises a logic circuit configured receive state information and to responsively generate signals identifying the wire index and path associated with the wire fault, the generated signals used to generate the set of wire steering control signals.

7. A method comprising:

generating a plurality of sets of m data bits, each set of m data bits corresponding to a valid transition codeword of a transition code, each valid transition codeword comprising n elements and c transitions, wherein any set of c−

1 transitions of the c transitions corresponds to a valid reduced-transition codeword, and wherein m, n, and c are integers greater than or equal to 2;

encoding the plurality of sets of m data bits into a sequence of valid transition codewords;

transmitting the sequence of valid transition codewords on n wires of an egress path, the egress path having a spare wire in addition to the n wires;

decoding the sequence of valid transition codewords into a plurality of sets of m received bits;

detecting two or more sets of m received bits as corresponding to valid reduced-transition codewords indicative of an egress wire fault, the valid reduced-transition codewords collectively forming a group of valid reduced-transition codewords associated with one of the n wires of the egress path associated with the egress wire fault; and

generating a plurality of sets of m response bits comprising (i) the detected two or more sets of m data bits and (ii) at least one set of m response bits corresponding to an egress fault indication codeword; and

encoding the plurality of sets of m response bits into a plurality of response codewords having n elements and responsively transmitting the response codewords via n wires of an ingress path.

8. The method of claim 7, wherein the path-fault indication codeword represents a valid transition codeword having TC number of transitions, wherein TC is an integer according to:

c<

TC or TC<

c−

1.

9. The method of claim 7, further comprising decoding the plurality of response codewords.

10. The method of claim 9, further comprising identifying a wire index of the egress wire fault based on the decoded plurality of response codewords.

11. The method of claim 9, wherein the wire index is identified by a combination of states, each state corresponding to a respective reduced-transition codeword of the group of reduced-transition codewords.

12. The method of claim 7, wherein the transition code is an FTTL4 code.

13. The method of claim 7, further comprising identifying a set of m data bits representing an invalid codeword, and suppressing the invalid codeword by substituting a set of m response bits representing a valid transition codeword having c transitions.

17. The system of claim 9, wherein the logic circuit comprises a plurality of AND gates, each AND gate having respective combinations of inverting and non-inverting inputs to implement a respective combination of the received state elements.

18. The method of claim 11, wherein the combination of states is determined using a logic AND gate receiving state outputs from a plurality of flip-flops.

19. The method of claim 7, further comprising rerouting an element of the valid transition codewords from the wire associated with the egress wire fault to the spare wire of the egress path.

20. The method of claim 19, wherein the element of the valid transition codewords is rerouted using steering logic comprising multiplexers.