Adjustable power rail multiplexing

• US 9,852,859 B2
• Filed: 12/28/2015
• Issued: 12/26/2017
• Est. Priority Date: 12/28/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Cao, Lipeng, Kumar, Dorav, Zafar, Bilal, Vilangudipitchai, Ramaprasath, Narayanan, Venkatasubramanian, Luo, Xi
• Primary Examiner(s): Luu, An
• Application Number:
  US14/981,183
• Publication Number:
  US 20170186576A1
• Time in Patent Office: 729 Days
• CPC Class Codes: H01H 47/00 Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption

Abstract

An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.

Claims

1. An integrated circuit comprising:

a first power rail;

a second power rail;

a load power rail;

multiple power-multiplexer tiles coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation, each power-multiplexer tile configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail; and

adjustment circuitry configured to adjust at least one order in which the multiple power-multiplexer tiles perform at least a portion of the power-multiplexing operation.

2. The integrated circuit of claim 1, wherein:

the power-multiplexing operation is effectuated across the chained arrangement of the multiple power-multiplexer tiles;

the power-multiplexing operation includes a disconnection portion and a connection portion;

the multiple power-multiplexer tiles are configured to perform the disconnection portion of the power-multiplexing operation in a sequential order; and

the adjustment circuitry is further configured to cause the multiple power-multiplexer tiles to perform the connection portion of the power-multiplexing operation in a non-sequential order.

3. The integrated circuit of claim 2, wherein the adjustment circuitry is further configured to enable at least one power-multiplexer tile of the multiple power-multiplexer tiles to perform the connection portion of the power-multiplexing operation out of an order that is determined by a series coupling of the chained arrangement of the multiple power-multiplexer tiles.

4. The integrated circuit of claim 3, wherein the adjustment circuitry is further configured to provide to the at least one power-multiplexer tile an input feedback control signal selected from a preset signal set to a logical high value or an output feedback control signal produced by a preceding power-multiplexer tile.

5. The integrated circuit of claim 4, wherein:

the at least one power-multiplexer tile is configured to connect the load power rail to the second power rail responsive to the input feedback control signal having the logical high value; and

the adjustment circuitry is further configured to select the preset signal as the input feedback control signal for the at least one power-multiplexer tile to enable the at least one power-multiplexer tile to couple the load power rail to the second power rail out of the order that is determined by the series coupling of the chained arrangement of the multiple power-multiplexer tiles.

6. The integrated circuit of claim 3, wherein the adjustment circuitry is further configured to provide to the at least one power-multiplexer tile an input feedback control signal that is set to a logical high value to enable the at least one power-multiplexer tile to couple the load power rail to the second power rail out of the order that is determined by the series coupling of the chained arrangement of the multiple power-multiplexer tiles.

7. The integrated circuit of claim 6, wherein the adjustment circuitry is further configured to provide a feedback adjustment signal that is tied to a preset value to cause the input feedback control signal to be coupled to a preset signal set to a logical high value.

8. The integrated circuit of claim 1, wherein:

the multiple power-multiplexer tiles are further configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail in at least one sequential order to avoid creation of a short-circuit current condition between the first power rail and the second power rail in one mode; and

the adjustment circuitry is further configured to enable adjustment of a duration for which the load power rail is coupled to both the first power rail and the second power rail in another mode by enabling one or more power-multiplexer tiles of the multiple power-multiplexer tiles to selectively couple the load power rail to the second power rail out of the at least one sequential order.

9. The integrated circuit of claim 8, wherein a length of the duration is controllable based on a number of intervening power-multiplexer tiles between one power-multiplexing tile that is last in the chained arrangement of the multiple power-multiplexer tiles and another power-multiplexer tile that is first to be enabled to couple the load power rail to the second power rail out of the at least one sequential order.

10. The integrated circuit of claim 1, wherein each power-multiplexer tile of the multiple power-multiplexer tiles includes:

a first switch configured to connect or disconnect the load power rail to or from the first power rail;

a second switch configured to connect or disconnect the load power rail to or from the second power rail; and

a delay control circuit configured to prevent the first switch and the second switch of a given power-multiplexer tile from being closed simultaneously.

11. The integrated circuit of claim 10, wherein the delay control circuit comprises self-timed circuitry that is independent of a periodic clock signal.

12. The integrated circuit of claim 1, wherein the adjustment circuitry is further configured to cause a temporal overlap region in which one power-multiplexer tile of the multiple power-multiplexer tiles is coupling the load power rail to the first power rail and another power-multiplexer tile of the multiple power-multiplexer tiles is coupling the load power rail to the second power rail.

13. The integrated circuit of claim 1, wherein:

the multiple power-multiplexer tiles comprise multiple first power-multiplexer tiles that form a first chained series of power-multiplexer tiles;

the integrated circuit further comprises a second chained series of power-multiplexer tiles including multiple second power-multiplexer tiles coupled in series in a chained arrangement and configured to jointly perform the power-multiplexing operation; and

the adjustment circuitry is further configured to establish a duration of a short-circuit current condition created between the first power rail and the second power rail by coordinating operation of the first chained series of power-multiplexer tiles and the second chained series of power-multiplexer tiles.

14. An integrated circuit comprising:

a first power rail;

a second power rail;

a load power rail;

multiple power-multiplexer tiles coupled in series in a chained arrangement and configured to perform a power-multiplexing operation including switching between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail, the power-multiplexing operation having at least one order that is determined by the series in which the multiple power-multiplexer tiles are coupled for the chained arrangement; and

adjustment means for adjusting the at least one order in which the multiple power-multiplexer tiles are to perform at least a portion of the power-multiplexing operation.

15. The integrated circuit of claim 14, wherein the adjustment means comprises means for establishing a duration that a short-circuit current condition exists between the first power rail and the second power rail across different power-multiplexer tiles during the power-multiplexing operation.

16. The integrated circuit of claim 14, wherein the adjustment means comprises means for enabling a particular power-multiplexer tile of the multiple power-multiplexer tiles to perform at least part of the power-multiplexing operation out of the at least one order.

17. The integrated circuit of claim 14, wherein the integrated circuit further comprises means for controlling a decoupling of the load power rail from the first power rail in a sequential order along the series in which the multiple power-multiplexer tiles are coupled for the chained arrangement.

18. The integrated circuit of claim 14, wherein the adjustment means comprises means for controlling a coupling of the load power rail to the second power rail in a selectable order.

19. The integrated circuit of claim 18, wherein the means for controlling the coupling comprises means for selecting a particular power-multiplexer tile of the multiple power-multiplexer tiles for switching out of a sequential order.

20. The integrated circuit of claim 19, wherein the means for selecting the particular power-multiplexer tile comprises means for forwarding a preset signal set to a logical high value, instead of an output feedback control signal produced by a preceding power-multiplexer tile, to the particular power-multiplexer tile to select the particular power-multiplexer tile.

21. A method for adjustable power rail multiplexing in an integrated circuit, the method comprising:

supplying power to a circuit load via a first power rail while a load power rail is coupled to the first power rail;

decoupling the load power rail from the first power rail as part of a power-multiplexing operation;

coupling the load power rail to a second power rail as part of the power-multiplexing operation;

supplying power to the circuit load via the second power rail while the load power rail is coupled to the second power rail; and

during the power-multiplexing operation, providing a signal to establish a duration of a short-circuit current condition between the first power rail and the second power rail.

22. The method of claim 21, wherein:

the decoupling comprises opening multiple first switches of multiple power-multiplexer tiles, the multiple first switches of multiple power-multiplexer tiles coupled between the first power rail and the load power rail; and

the coupling comprises closing multiple second switches of the multiple power-multiplexer tiles, the multiple second switches coupled between the second power rail and the load power rail.

23. The method of claim 21, wherein:

the decoupling comprises propagating a power rail selection signal through multiple power-multiplexer tiles coupled in series in a chained arrangement to a last power-multiplexer tile of the chained arrangement; and

the coupling comprises propagating a feedback control signal through the chained arrangement of the multiple power-multiplexer tiles starting from the last power-multiplexer tile of the chained arrangement.

24. The method of claim 21, wherein the providing the signal comprises providing a feedback adjustment signal to a particular power-multiplexer tile of multiple power-multiplexer tiles to advance an occurrence of the coupling of the load power rail to the second power rail at the particular power-multiplexer tile.

25. The method of claim 24, wherein the providing the feedback adjustment signal comprises selecting as an input feedback control signal for the particular power-multiplexer tile a preset signal set to a logical high value instead of an output feedback control signal produced by another power-multiplexer tile that is consecutive with the particular power-multiplexer tile and precedes the particular power-multiplexer tile in a feedback direction along a series in which the multiple power-multiplexer tiles are coupled in a chained arrangement.

26. The method of claim 21, wherein the providing the signal comprises providing a preset signal set to a logical high value to cause a feedback control signal input of a particular power-multiplexer tile of multiple power-multiplexer tiles to have a logical high value so as to advance an occurrence of the coupling of the load power rail to the second power rail at the particular power-multiplexer tile.

27. The method of claim 21, wherein the supplying power to the circuit load via the first power rail and the supplying power to the circuit load via the second power rail comprise simultaneously supplying power to the circuit load via the first power rail at one power-multiplexer tile and supplying power to the circuit load via the second power rail at another power-multiplexer tile.

28. An apparatus comprising:

a circuit load;

a first power rail;

a second power rail;

a load power rail that is coupled to the circuit load;

multiple power-multiplexer tiles disposed in a chained arrangement and configured to propagate a power rail selection signal between consecutive power-multiplexer tiles in a first direction along the chained arrangement to disconnect the first power rail from the load power rail and to propagate a feedback control signal between consecutive power-multiplexer tiles in a second direction along the chained arrangement to connect the second power rail to the load power rail; and

adjustment circuitry configured to enable establishment of a timing of an occurrence of a connection of the second power rail to the load power rail at a particular power-multiplexer tile of the multiple power-multiplexer tiles.

29. The apparatus of claim 28, wherein:

the second direction is a reverse of the first direction along the chained arrangement;

the multiple power-multiplexer tiles include a last power-multiplexer tile along the chained arrangement; and

the adjustment circuitry is further configured to advance the timing of the occurrence of the connection of the second power rail to the load power rail at the particular power-multiplexer tile so as to transpire prior to an occurrence of a connection of the second power rail to the load power rail at the last power-multiplexer tile.

30. The apparatus of claim 28, wherein:

the second direction is a reverse of the first direction along the chained arrangement;

the multiple power-multiplexer tiles include a last power-multiplexer tile in the first direction at a terminating end of the chained arrangement; and

the adjustment circuitry is further configured to advance the timing of the occurrence of the connection of the second power rail to the load power rail at the particular power-multiplexer tile so as to transpire prior to an occurrence of a disconnection of the first power rail from the load power rail at the last power-multiplexer tile.