Integrated circuit device body bias circuits and methods

• US 9,853,019 B2
• Filed: 10/28/2016
• Issued: 12/26/2017
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Clark, Lawrence T., Kidd, David A., Kuo, Augustine
• Primary Examiner(s): Hiltunen, Thomas J
• Application Number:
  US15/337,876
• Publication Number:
  US 20170047100A1
• Time in Patent Office: 424 Days
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H02M 3/076 the clock signals being boosted to a value being higher than the input voltage value
• CPC Class Codes: H02M 3/078 with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converters
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Claims

1. A method, comprising:

supplying a first power supply voltage for a charge pump circuit that generates a global body bias voltage;

generating a local body bias voltage from the global body bias voltage;

waiting for a predetermined delay after the local body bias voltage reaching and being stable at a predetermined value, and then supplying a second power supply voltage applied for transistors having the local body bias voltage while the local body bias voltage is stable at the predetermined value, the second power supply voltage being lower than the first power supply voltage.

2. The method of claim 1, further including:

in response to at least one local event and in response to a global event, coupling bodies of the transistors to a collapse voltage that tracks the first power supply voltage.

3. The method of claim 1, wherein:

the transistors including deeply depleted channel (DDC) transistors, each DDC transistor comprises a body with a screening region of a dopant concentration of no less than 1×

10¹⁸ dopant atoms/cm³ formed below a transistor channel.