Three-dimensional memory device having integrated support and contact structures and method of making thereof

• US 9,853,038 B1
• Filed: 01/20/2017
• Issued: 12/26/2017
• Est. Priority Date: 01/20/2017
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Cui, Zhixin
• Primary Examiner(s): Vu, David
• Application Number:
  US15/411,126
• Time in Patent Office: 340 Days
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Memory openings and support openings are formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. The support openings are laterally expanded by laterally recessing the insulating layers with respect to the sacrificial material layers. The laterally expanded support openings are filled with a combination of a dielectric material and a sacrificial fill material to form support pillar structures. After forming memory films and channels in the memory openings, the sacrificial material layers are replaced with electrically conductive layers while the support pillar structures provide structural support to the insulating layers. The sacrificial fill material is replaced with contact via structures to form integrated support and contact structures.

Claims

1. A three-dimensional memory device comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film; and

at least one integrated support and contact structure, wherein each of the at least one integrated support and contact structure includes;

a contact via structure contacting a top surface of a respective one of the electrically conductive layers;

a tubular dielectric liner that laterally surrounds the contact via structure; and

a fin-containing dielectric pillar underlying the respective contact via structure and including a respective dielectric fin that laterally protrudes outward at each level of one or more underlying insulating layers that underlies a horizontal plane including a bottom surface of the contact via structure.

2. The three-dimensional memory device of claim 1, wherein the tubular dielectric liner and the fin-containing dielectric pillar comprise a same dielectric material.

3. The three-dimensional memory device of claim 1, wherein a top surface of the fin-containing dielectric pillar contacts the bottom surface of the contact via structure.

4. The three-dimensional memory device of claim 1, wherein:

the respective one of the electrically conductive layers includes an opening therethrough; and

the contact via structure contacts an upper portion of a sidewall of the respective one of the electrically conductive layers inside the opening.

5. The three-dimensional memory device of claim 4, wherein the fin-containing dielectric pillar contacts a lower portion of a sidewall of the respective one of the electrically conductive layers inside the opening.

6. The three-dimensional memory device of claim 1, further comprising:

a terrace region including stepped surfaces of the alternating stack; and

a retro-stepped dielectric material portion overlying the terrace region,

wherein the tubular dielectric liner is laterally surrounded by the retro-stepped dielectric material region.

7. The three-dimensional memory device of claim 6, wherein:

the tubular dielectric liner includes a flaring region that protrudes outward with a convex sidewall that adjoins an underlying vertically extending region; and

a top surface of the tubular dielectric liner is coplanar with a top surface of the retro-stepped dielectric material portion.

8. The three-dimensional memory device of claim 6, wherein:

each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack in the terrace region;

the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and

the at least one integrated support and contact structure extends through a respective horizontal portion of the stepped surfaces.

9. The three-dimensional memory device of claim 1, wherein:

each one of the memory stack structures contacts a top surface of a respective instance of a semiconductor pedestal; and

the fin-containing dielectric pillar contacts an additional instance of the semiconductor pedestal.

10. The three-dimensional memory device of claim 1, further comprising a backside blocking dielectric layer disposed between each neighboring pair of an electrically conductive layer and an insulating layer and extending from a bottommost layer within the alternating stack to a topmost layer within the alternating stack, wherein the fin-containing dielectric pillar is laterally spaced from a subset of the electrically conductive layers by the backside blocking dielectric layer.

11. The three-dimensional memory device of claim 1, wherein:

the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;

the substrate comprises a silicon substrate;

the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.