Three dimension integrated circuits employing thin film transistors

• US 9,853,053 B2
• Filed: 12/23/2014
• Issued: 12/26/2017
• Est. Priority Date: 09/10/2012
• Status: Active Grant

• Current Assignee: Tacho Holdings, LLC
• Original Assignee: 3B Technologies, Inc.
• Inventors: Lupino, James John, Agan, Tommy Allen
• Primary Examiner(s): Armand, Marc
• Application Number:
  US14/580,240
• Publication Number:
  US 20150249096A1
• Time in Patent Office: 1,099 Days
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/165 Auxiliary circuits
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

An integrated circuit which enables lower cost yet provides superior performance compared to standard silicon integrated circuits by utilizing thin film transistors (TFTs) fabricated in BEOL. Improved memory circuits are enabled by utilizing TFTs to improve density and access in a three dimensional circuit design which minimizes die area. Improved I/O is enabled by eliminating the area on the surface of the semiconductor dedicated to I/O and allowing many times the number of I/O available. Improved speed and lower power are also enabled by the shortened metal routing lines and reducing leakage.

Claims

1. An integrated circuit device, comprising

at least one memory array layer arranged in a matrix and comprising a plurality of parallel first conductive lines, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of memory cells, each memory cell being disposed at an intersection region of the conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance,

whereby each conductive line of the first conductive lines or the second conductive lines or both first and second conductive lines, is electrically coupled to at least one thin film transistor of a thin film transistor layer, which is positioned directly above the memory array layer.

2. The device according to claim 1 whereby the memory cells are selected from the group consisting of NRAM-type, FeRAM-type, RRAM-type, MRAM-type, CBRAM-type, and PCRAM-type.

3. The device according to claim 1 whereby the memory array layer is embedded memory of a microprocessor, microcontroller, FPGA, GPU, PLD, ASIC, ASSP, DSP, or other integrated circuit.

4. The device according to claim 1 further comprising a bidirectional selector switch disposed between each memory cell and one of said first or second conductive lines.

5. The device according to claim 1, wherein the at least one memory array layer comprises at least two memory array layers separated from each other in the vertical direction.

6. The device according to claim 1, whereby a buffer memory is employed to enable I/O from an external source at a higher clock speed than the I/O to a nonvolatile memory array.

7. The integrated circuit device of claim 1 wherein a first one of said at least one thin film transistor is of a carbon nanotube type.

8. The integrated circuit device of claim 1 wherein the first one of said at least one thin film transistor is of an amorphous oxide semiconductor type.

9. The device according to claim 5 whereby at least a first memory array layer of the at least two memory array layers is a resistance random access memory array.

10. The device according to claim 5 whereby at least one of said at least two memory array layers is embedded memory of a microprocessor, microcontroller, FPGA, GPU, PLD, ASIC, ASSP, DSP, or other integrated circuit.

11. The device according to claim 5, whereby a buffer memory is employed to enable I/O from an external source at a higher clock speed than the I/O to a nonvolatile memory array.

12. The device according to claim 5, wherein the at least two memory array layers comprises a plurality of logic blocks comprising thin film transistors and interconnects, each one of the plurality of logic blocks being disposed between the layers in the vertical direction.

13. The device according to claim 12 whereby the device comprises either a microprocessor, microcontroller, FPGA, GPU, PLD, ASIC, ASSP, DSP, MEMS or a hybrid thereof.

14. The device according to claim 12 whereby the device comprises an energy storage device, display, RF device or image sensor.

15. The integrated circuit device of claim 8 wherein the first one of said at least one thin film transistor is either of an IGZO-type or a ZnO-type.

16. The integrated circuit device of claim 8 wherein the first one of said at least one thin film transistor is of a SnO2-type.

17. The integrated circuit device of claim 8 wherein the first one of said at least one thin film transistor is of a MoS2-type.