Semiconductor device and manufacturing method thereof

• US 9,853,066 B2
• Filed: 07/27/2015
• Issued: 12/26/2017
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Miyake, Hiroyuki
• Primary Examiner(s): Ingham, John C
• Application Number:
  US14/809,767
• Publication Number:
  US 20150333090A1
• Time in Patent Office: 883 Days
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/13069 Thin film transistor [TFT]

Abstract

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

Claims

1. A semiconductor device comprising:

an inverter comprising a first transistor and a second transistor over a substrate, each of the first transistor and the second transistor comprising;

a first electrode layer;

an oxide semiconductor layer with a first insulating film interposed therebetween, the oxide semiconductor layer comprising indium, zinc, and one or more metal elements selected from gallium, aluminum, manganese, cobalt, and tin;

a second electrode layer on the oxide semiconductor layer;

a third electrode layer on the oxide semiconductor layer; and

a fourth electrode layer over the first electrode layer with at least the oxide semiconductor layer and a second insulating film interposed therebetween,

wherein the third electrode layer of the first transistor is electrically connected to the second electrode layer of the second transistor,

wherein one of the first electrode layer and the fourth electrode layer of the second transistor is electrically connected to the second electrode layer of the second transistor, and

wherein the oxide semiconductor layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer over the first semiconductor layer.

2. The semiconductor device according to claim 1, wherein a voltage is applied to the first electrode layer of the first transistor, the fourth electrode layer of the first transistor, and the first electrode layer and the fourth electrode layer of the second transistor respectively.

3. The semiconductor device according to claim 1, wherein the first transistor is an enhancement transistor and the second transistor is a depletion transistor.

4. The semiconductor device according to claim 1,

wherein the fourth electrode layer is a main gate electrode in the first transistor, and

wherein the fourth electrode layer is a main gate electrode in the second transistor.

5. The semiconductor device according to claim 1, wherein an energy gap of an oxide semiconductor included in the oxide semiconductor layer is greater than or equal to 2 eV.

6. The semiconductor device according to claim 1, wherein the first transistor has a different threshold value from the second transistor.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor layer of the first transistor and the oxide semiconductor layer of the second transistor have the same composition and the same purity.

8. The semiconductor device according to claim 1, wherein the fourth electrode layer of the second transistor is electrically connected to the second electrode layer of the second transistor.

9. An electronic device comprising the semiconductor device according to claim 1.

10. A semiconductor device comprising:

an inverter comprising a first transistor and a second transistor over a substrate, each of the first transistor and the second transistor comprising;

a first electrode layer;

an oxide semiconductor layer with a first insulating film interposed therebetween, the oxide semiconductor layer comprising indium, zinc, and one or more metal elements selected from gallium, aluminum, manganese, cobalt, and tin;

a second electrode layer on the oxide semiconductor layer;

a third electrode layer on the oxide semiconductor layer; and

a fourth electrode layer over the first electrode layer with at least the oxide semiconductor layer and a second insulating film interposed therebetween,

wherein the third electrode layer of the first transistor is electrically connected to the second electrode layer of the second transistor,

wherein one of the first electrode layer and the fourth electrode layer of the second transistor is electrically connected to the second electrode layer of the second transistor,

wherein the oxide semiconductor layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer over the first semiconductor layer,

wherein the second oxide semiconductor layer comprises a crystalline region comprising crystals, and

wherein c-axes of the crystals are oriented substantially in a direction perpendicular to a surface of the oxide semiconductor layer.

11. The semiconductor device according to claim 10, wherein a voltage is applied to the first electrode layer of the first transistor, the fourth electrode layer of the first transistor, and the first electrode layer and the fourth electrode layer of the second transistor respectively.

12. The semiconductor device according to claim 10, wherein the first transistor is an enhancement transistor and the second transistor is a depletion transistor.

13. The semiconductor device according to claim 10,

wherein the fourth electrode layer is a main gate electrode in the first transistor, and

wherein the fourth electrode layer is a main gate electrode in the second transistor.

14. The semiconductor device according to claim 10, wherein an energy gap of an oxide semiconductor included in the oxide semiconductor layer is greater than or equal to 2 eV.

15. The semiconductor device according to claim 10, wherein the first transistor has a different threshold value from the second transistor.

16. The semiconductor device according to claim 10, wherein the oxide semiconductor layer of the first transistor and the oxide semiconductor layer of the second transistor have the same composition and the same purity.

17. The semiconductor device according to claim 10, wherein the fourth electrode layer of the second transistor is electrically connected to the second electrode layer of the second transistor.

18. An electronic device comprising the semiconductor device according to claim 10.