Semiconductor device and structure

• US 9,853,089 B2
• Filed: 08/01/2016
• Issued: 12/26/2017
• Est. Priority Date: 10/12/2009
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Beinglass, Israel, Wurman, Zeev
• Primary Examiner(s): Pert, Evan
• Application Number:
  US15/224,929
• Publication Number:
  US 20160343774A1
• Time in Patent Office: 512 Days
• CPC Class Codes: G03F 9/7076 Mark details, e.g. phase grating mark, temporary mark
• CPC Class Codes: G03F 9/7084 Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.

Claims

1. A semiconductor device, comprising:

a first memory cell comprising a first transistor;

a second memory cell comprising a second transistor,

wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor; and

a plurality of junctionless transistors,

wherein at least one of said junctionless transistors controls access to at least one of said memory cells.

2. A semiconductor according to claim 1,

wherein said junctionless transistors each comprise a single crystal channel.

3. A semiconductor according to claim 1,

wherein said first transistor comprises silicon and germanium atoms.

4. A semiconductor according to claim 1, further comprising:

an electrically controlled resistive structure connected to a source or a drain of said first transistor.

5. A semiconductor according to claim 1,

wherein said first transistor comprises a silicided source and drain.

6. A semiconductor according to claim 1, further comprising:

a third memory cell, and

an electronic circuit adapted to remap said third memory cell.

7. A semiconductor according to claim 1, further comprising:

a memory peripherals circuits overlaying said second transistor or underneath said first transistor.

8. A semiconductor device, comprising:

an electrically controlled resistive structure;

a first memory cell comprising a first transistor; and

a second memory cell comprising a second transistor,

wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor, and

wherein said electrically controlled resistive structure could be set to conduct a signal to said first transistor.

9. A semiconductor according to claim 8,

wherein said first transistor comprises a single crystal channel.

10. A semiconductor according to claim 8,

wherein said first transistor comprises a silicon and germanium atoms.

11. A semiconductor according to claim 8,

wherein said first transistor comprises a silicided source and drain.

12. A semiconductor according to claim 8,

wherein access to said first memory cell is controlled by at least one junctionless transistor.

13. A semiconductor according to claim 8, further comprising:

a memory peripherals circuits overlaying said second transistor or underneath said first transistor.

14. A semiconductor according to claim 8, further comprising:

a memory control line,

wherein said memory control line has a direct contact with said first transistor.

15. A semiconductor device, comprising:

a first memory cell comprising a first transistor; and

a second memory cell comprising a second transistor,

wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor, and

wherein said first transistor comprises a silicided source and drain.

16. A semiconductor according to claim 15,

wherein said first transistor comprises a single crystal channel.

17. A semiconductor according to claim 15,

wherein said first transistor comprises silicon and germanium atoms.

18. A semiconductor according to claim 15, further comprising:

a memory peripherals circuits overlaying said second transistor or underneath said first transistor.

19. A semiconductor according to claim 15,

wherein access to said first memory cell is controlled by at least one junctionless transistor.

20. A semiconductor according to claim 15, further comprising:

a memory control line,

wherein said memory control line has direct contact with said first transistor.