Adaptive charge balanced MOSFET techniques

• US 9,853,140 B2
• Filed: 12/31/2012
• Issued: 12/26/2017
• Est. Priority Date: 12/31/2012
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Tipirneni, Naveen, Pattanayak, Deva N.
• Primary Examiner(s): Carter, Michael
• Assistant Examiner(s): Alam, Mohammed R
• Application Number:
  US13/732,284
• Publication Number:
  US 20140183624A1
• Time in Patent Office: 1,821 Days
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An adaptive charge balanced MOSFET device includes a field plate stacks, a gate structure, a source region, a drift region and a body region. The gate structure includes a gate region surrounded by a gate insulator region. The field plate stack includes a plurality of field plate insulator regions, a plurality of field plate regions, and a field ring region. The plurality of field plates are separated from each other by respective field plate insulators. The body region is disposed between the gate structure, the source region, the drift region and the field ring region. Each of two or more field plates are coupled to the field ring.

Claims

1. An apparatus comprising:

a drain region;

a drift region disposed on the drain region;

a plurality of body regions disposed on the drift region opposite the drain region;

a plurality of source regions disposed on the plurality of body regions opposite the drift region;

a plurality of gate structures, wherein each gate structure includes;

a plurality of substantially parallel elongated gate regions extending through the plurality of source regions and the plurality of body regions and extending partially into the drift region; and

a plurality of gate insulator regions each disposed between a respective one of the plurality of gate regions and the plurality of source regions, the plurality of body regions and the drift region; and

a plurality of field plate structures, wherein each field plate structure is disposed through the body regions and extending into the drift region, wherein each gate structure is disposed between a set of field plate structures, and wherein each field plate structure includes;

a plurality of field plate insulator regions;

a plurality of field plate regions, wherein the plurality of field plate regions are interspersed between the plurality of field plate insulator regions; and

a field ring region disposed between the plurality of field plate regions and the adjacent drift regions, and wherein regions of a set of field plates are laterally separated from the field ring region by the plurality of field plate insulator regions and other regions of the set of field plates are coupled to the field ring region;

wherein the plurality of gate structures are adjacent the plurality of source regions, the plurality of body regions and the drift regions.

2. The apparatus according to claim 1, wherein:

the drain region comprises a heavily n-doped semiconductor;

the drift region comprises a moderate n-doped semiconductor;

the plurality of body regions comprise a moderately p-doped semiconductor;

the plurality of source regions comprise a heavily n-doped semiconductor;

the plurality of field plate regions comprise a heavily p-doped semiconductor; and

the field ring region comprises a heavily p-doped semiconductor.

3. The apparatus according to claim 1, wherein:

the drain region comprises a heavily p-doped semiconductor;

the drift region comprises a moderately p-doped semiconductor;

the plurality of body regions comprise a moderately n-doped semiconductor;

the plurality of source regions comprise a heavily p-doped semiconductor;

the plurality of field plate regions comprise a heavily n-doped semiconductor;

the field ring region comprises a heavily n-doped semiconductor.

4. The apparatus according to claim 1, wherein the field ring region comprises multiple portions wherein two or more portions of the field ring region are coupled to a corresponding field plate region.

5. The apparatus according to claim 1, further comprising a source/body/field plate contact disposed on the source region, the body region and one of the plurality of field plate regions.

6. The apparatus according to claim 1, wherein the plurality of field plate regions are in Schottky contact with the drift region increasing a breakdown voltage of the apparatus as compared to an ohmic contact.

7. A apparatus comprising:

a field plate stack including;

a plurality of field plate insulator regions;

a plurality of field plate regions, wherein the plurality of field plate regions are interspersed between the plurality of field plate insulator regions; and

a field ring region, wherein the plurality of field plate regions are coupled to the field ring region, wherein a thickness of one of the plurality of field plate insulator regions and a thickness of a contact area between one of the plurality of field plate regions and the field ring region are selected so that the one of the plurality of field plate regions and another one of the plurality of field plate regions float to a different potential when a drain voltage is greater than a pinch-off voltage;

a gate structure including a gate region surrounded by a gate insulator region;

a source region;

a drift region; and

a body region coupled to the source region, the drift region and the field ring region.

8. The apparatus according to claim 7, wherein the field ring region comprises multiple portions wherein two or more portions of the field ring region each couple a corresponding field plate region to an adjacent portion of the body region.

9. The apparatus according to claim 7, wherein:

the drift region comprises epitaxial silicon moderately doped with phosphorous or arsenic;

the body region comprises silicon moderately doped with boron;

the source region comprises silicon heavily doped with phosphorous or arsenic;

the gate region comprises polysilicon heavily doped with phosphorous or arsenic;

the plurality of field plate regions comprise polysilicon heavily doped with boron; and

the field ring region comprises epitaxial silicon heavily doped with boron.

10. The apparatus according to claim 7, wherein:

the drift region comprises epitaxial silicon moderately doped with boron;

the body region comprises silicon moderately doped with phosphorous or arsenic;

the source region comprises silicon heavily doped with boron;

the gate region comprises polysilicon heavily doped with boron;

the plurality of field plate regions comprise polysilicon heavily doped with phosphorous or arsenic; and

the field ring region comprises epitaxial silicon heavily doped with phosphorous or arsenic.

11. The apparatus according to claim 7, wherein a depth of the field plate stack is greater than a depth of the gate structure.

12. A metal-oxide-semiconductor field effect transistor comprising:

a field plate stack including;

a plurality of field plate insulator regions;

a plurality of field plate regions comprising polysilicon heavily doped with boron, phosphorous, or arsenic, wherein the plurality of field plate regions are interspersed between the plurality of field plate insulator regions; and

a field ring region comprising epitaxial silicon heavily doped with boron, phosphorous, or arsenic, wherein the plurality of field plate regions are coupled to the field ring region, wherein a thickness of one of the plurality of field plate insulator regions and a thickness of a contact area between one of the plurality of field plate regions and the field ring region are selected so that the one of the plurality of field plate regions and another one of the plurality of field plate regions float to a different potential when a drain voltage is greater than a pinch-off voltage;

a gate structure including a gate region surrounded by a gate insulator region, the gate region comprising polysilicon heavily doped with phosphorous, arsenic or boron;

a source region comprising silicon heavily doped with phosphorous, arsenic or boron;

a drift region comprising epitaxial silicon moderately doped with phosphorous, arsenic or boron; and

a body region coupled to the source region, the drift region and the field ring region;

the body region comprises silicon moderately doped with boron, phosphorous or arsenic.

13. The metal-oxide-semiconductor field effect transistor according to claim 12, wherein the field ring region comprises multiple portions wherein two or more portions of the field ring region each couple a corresponding field plate region to an adjacent portion of the body region.

14. The metal-oxide-semiconductor field effect transistor according to claim 12, wherein a depth of the field plate stack is greater than a depth of the gate structure.