Power MOSFET with metal filled deep source contact

• US 9,853,144 B2
• Filed: 06/02/2016
• Issued: 12/26/2017
• Est. Priority Date: 01/18/2016
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lin, Furen, Baiocchi, Frank, Liu, Yunlong, Liu, Lark, Lv, Tianping, Lin, Peter, Lin, Ho
• Primary Examiner(s): STARK, JARRETT J
• Application Number:
  US15/171,136
• Publication Number:
  US 20170207335A1
• Time in Patent Office: 572 Days
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

Claims

1. A method of fabricating a planar gate power metal-oxide-semiconductor field effect transistor (power MOSFET), comprising:

providing a planar gate power MOSFET die including a plurality of transistor cells (cells) including a first cell and at least a second cell formed on a substrate having a semiconductor surface doped a first conductivity type, said first cell having a first gate stack and said second cell having a second gate stack, each said gate stack including a gate electrode on a gate dielectric over a body region, a trench having an aspect ratio of at least 3 extending down from a top side of said semiconductor surface between said first and said second gate stack providing a source contact (SCT) from said substrate to a source doped a second conductivity type, a field plate (FP) over said gate stacks extending to provide a liner for said trench, said trench having a refractory or platinum-group metal (PGM) metal filler (metal filler) within, and a drain doped said second conductivity type in said semiconductor surface on a side of said gate stacks opposite said trench, wherein said trench is formed by an etching process using self-alignment provided by said gate stacks;

first etching of said metal filler for removing said metal filler along a sidewall of said FP over said drain and removing a portion of said metal filler in said trench;

depositing said metal filler including to fill said trench, and

second etching of said metal filler.

2. The method of claim 1, wherein said metal filler comprises tungsten (W).

3. The method of claim 1, wherein said metal filler comprises Ta, Pt, or Pd.

4. The method of claim 1, wherein said gate electrode comprises a metal silicide (WSi2) on polysilicon.

5. The method of claim 1, wherein said substrate comprises a p+ substrate and said semiconductor surface comprises a p-epitaxial layer, and wherein said power MOSFET comprises NMOS.

6. The method of claim 1, wherein said substrate comprises an n+ substrate and said semiconductor surface comprises an n-epitaxial layer, and wherein said power MOSFET comprises PMOS.

7. The method of claim 1, wherein said first etching and said second etching both comprise plasma etching.

8. The method of claim 1, wherein said FP comprises at least one refractory metal layer.

9. The method of claim 1 further comprising:

forming a substrate contact region at a bottom of said SCT after forming said trench, said substrate contact region being doped said first conductivity type.

10. The method of claim 1, wherein said first etching further comprises increasing a distance from a boundary of the FP to a boundary of the drain.

11. The method of claim 1, wherein said first etching further comprises reducing a probability of FP bridging the source to the drain.

12. A method of fabricating a planar gate power metal-oxide-semiconductor field effect transistor (power MOSFET), comprising:

providing a planar gate power MOSFET die including a plurality of transistor cells (cells) including a first cell and at least a second cell formed on a substrate having a semiconductor surface doped a first conductivity type, said first cell having a first gate stack and said second cell having a second gate stack, each said gate stack including a gate electrode on a gate dielectric over a body region, a trench having an aspect ratio of at least 3 extending down from a top side of said semiconductor surface between said first and said second gate stack providing a source contact (SCT) from said substrate to a source doped a second conductivity type, a field plate (FP) over said gate stacks extending to provide a liner for said trench, said trench having a refractory or platinum-group metal (PGM) metal filler (metal filler) within, and a drain doped said second conductivity type in said semiconductor surface on a side of said gate stacks opposite said trench, wherein said trench is formed by an etching process using self-alignment provided by said gate stacks;

first etching of said metal filler;

depositing said metal filler including to fill said trench, and

second etching of said metal filler.

13. The method of claim 12, wherein said first etching of said metal filler removes said metal filler along a sidewall of said FP over said drain and removing a portion of said metal filler in said trench.

14. The method of claim 12, wherein said metal filler comprises tungsten (W).

15. The method of claim 12, wherein said metal filler comprises Ta, Pt, or Pd.

16. The method of claim 12, wherein said gate electrode comprises a metal silicide (WSi2) on polysilicon.

17. The method of claim 12, wherein said substrate comprises a p+ substrate and said semiconductor surface comprises a p-epitaxial layer, and wherein said power MOSFET comprises NMOS.

18. The method of claim 12, wherein said substrate comprises an n+ substrate and said semiconductor surface comprises an n-epitaxial layer, and wherein said power MOSFET comprises PMOS.

19. The method of claim 12, wherein said first etching and said second etching both comprise plasma etching.

20. The method of claim 12, wherein said FP comprises at least one refractory metal layer.

21. The method of claim 12 further comprising:

forming a substrate contact region at a bottom of said SCT after forming said trench, said substrate contact region being doped with said first conductivity type.

22. The method of claim 12, wherein said first etching comprises at least one of:

increasing a distance from a boundary of the FP to a boundary of the drain and reducing a probability of FP bridging the source to the drain.