Source/drain contacts for non-planar transistors
First Claim
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1. A microelectronic device, comprising:
- a silicon-containing non-planar transistor fin;
a source/drain region in the silicon-containing non-planar fin;
a source/drain contact adjacent the source/drain region, wherein the source/drain contact comprises a conductive contact material and a titanium-containing contact interface layer disposed between conductive contact material and the source/drain region;
a titanium silicide interface disposed between the source/drain region and the titanium-containing contact interface layer; and
a non-planar transistor gate over the non-planar transistor fin, wherein the non-planar transistor gate comprises a gate electrode recessed between gate spacers and a capping structure disposed on the recessed gate electrode between the gate spacers, and wherein the titanium-containing contact interface layer abuts at least a portion of one non-planar transistor gate spacer and/or abuts at least a portion of the capping structure.
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Abstract
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.
83 Citations
16 Claims
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1. A microelectronic device, comprising:
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a silicon-containing non-planar transistor fin; a source/drain region in the silicon-containing non-planar fin; a source/drain contact adjacent the source/drain region, wherein the source/drain contact comprises a conductive contact material and a titanium-containing contact interface layer disposed between conductive contact material and the source/drain region; a titanium silicide interface disposed between the source/drain region and the titanium-containing contact interface layer; and a non-planar transistor gate over the non-planar transistor fin, wherein the non-planar transistor gate comprises a gate electrode recessed between gate spacers and a capping structure disposed on the recessed gate electrode between the gate spacers, and wherein the titanium-containing contact interface layer abuts at least a portion of one non-planar transistor gate spacer and/or abuts at least a portion of the capping structure. - View Dependent Claims (2, 3)
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4. A method of fabricating a microelectronic device, comprising:
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forming a silicon-containing non-planar transistor fin; forming a source/drain region in the silicon-containing non-planar fin; forming a dielectric material over the source/drain region; forming a contact opening through the dielectric material to expose a portion of the source/drain region; conformally depositing a titanium-containing contact interface layer within the contact opening to abut the source/drain region; depositing a conductive contact material within the contact opening to abut the titanium-containing contact interface layer; and forming a titanium silicide interface between the source/drain region and the titanium-containing contact interface layer. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A microelectronic device, comprising:
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a silicon-containing non-planar transistor fin; a source/drain region in the silicon-containing non-planar fin; a source/drain contact adjacent the source/drain region, wherein the source/drain contact comprises a conductive contact material and a titanium-containing contact interface layer disposed between conductive contact material and the source/drain region, wherein the titanium-containing contact interface layer comprises substantially pure titanium; a titanium silicide interface disposed between the source/drain region and the titanium- containing contact interface layer; and a non-planar transistor gate over the non-planar transistor fin, wherein the non-planar transistor gate comprises a gate electrode recessed between gate spacers and a capping structure disposed on the recessed gate electrode between the gate spacers, and wherein the titanium-containing contact interface layer abuts at least a portion of one non-planar transistor gate spacer and/or abuts at least a portion of the capping structure. - View Dependent Claims (15, 16)
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Specification