Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
First Claim
1. A method of data communications, comprising:
- receiving a plurality of data signals from a plurality of data lanes of a data communications link in accordance with a double data rate clock signal received from a timing lane of the data communications link, wherein each transition of the double data rate clock signal is aligned with a boundary between two data periods;
detecting a first-occurring transition on the data communications link at a boundary between a first data period and a second data period, whether the first-occurring transition occurs in a data signal carried on a data lane or in the double data rate clock signal, by comparing signaling state of the data communication link corresponding to the first data period with signaling state of the data communication link corresponding to the second data period;
generating an edge on a receiver clock signal based on the first-occurring transition; and
capturing data received from the plurality of data lanes using the receiver clock signal.
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Abstract
System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.
157 Citations
26 Claims
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1. A method of data communications, comprising:
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receiving a plurality of data signals from a plurality of data lanes of a data communications link in accordance with a double data rate clock signal received from a timing lane of the data communications link, wherein each transition of the double data rate clock signal is aligned with a boundary between two data periods; detecting a first-occurring transition on the data communications link at a boundary between a first data period and a second data period, whether the first-occurring transition occurs in a data signal carried on a data lane or in the double data rate clock signal, by comparing signaling state of the data communication link corresponding to the first data period with signaling state of the data communication link corresponding to the second data period; generating an edge on a receiver clock signal based on the first-occurring transition; and capturing data received from the plurality of data lanes using the receiver clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus, comprising:
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a processing circuit configured to; receive a plurality of data signals from a plurality of data lanes of a data communications link in accordance with a double data rate clock signal received from a timing lane of the data communications link, wherein each transition of the double data rate clock signal is aligned with a boundary between two data periods; store signaling state of the data communication link corresponding to the first data period; detect a first-occurring transition on the data communications link at a boundary between a first data period and a second data period, whether the first-occurring transition occurs in a data signal carried on a data lane or in the double data rate clock signal, by comparing the stored signaling state of the data communication link corresponding to the first data period with signaling state of the data communication link corresponding to the second data period; generate an edge on a receiver clock signal based on the first-occurring transition; and capture data received from the plurality of data lanes using the receiver clock signal. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A clock recovery circuit, comprising:
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a plurality of latches configured to store a first signaling state of a plurality of lanes of a data communication link, the plurality of lanes including a timing lane and at least one data lane; a comparator configured to compare the first signaling state with a second signaling state representing a current signaling state of the plurality of lanes of the data communication link; and a pulse generation circuit adapted to provide a pulse responsive to a change in output of the comparator corresponding to a first-occurring transition in a double data rate clock signal carried on the timing lane or in a data signal carried in the at least one data lane, wherein each transition of the double data rate clock signal is aligned with a boundary between two data periods of the data signal; and a clock generation circuit that generates a sampling clock from pulses provided by the pulse generation circuit, the sampling clock being configured to capture data from the at least one data lane, wherein the plurality of latches replaces the first signaling state with the second signaling state after termination of the pulse. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A clock recovery method, comprising:
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storing a first signaling state of a plurality of lanes of a data communication link as a previous signaling state, the plurality of lanes including a timing lane and at least one data lane; detecting a first-occurring transition in a double data rate clock signal carried on the timing lane or in a data signal carried in the at least one data lane by comparing the previous signaling state with a second signaling state representing a current signaling state of the plurality of lanes of the data communication link, wherein each transition of the double data rate clock signal is aligned with a boundary between two data periods of the data signal; and generating a pulse when the first-occurring transition is detected; using the pulse to generate a sampling clock configured to capture data from the at least one data lane; and storing the second signaling state as the previous signaling state after termination of the pulse. - View Dependent Claims (22, 23, 24, 25, 26)
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Specification