Continuous time linear equalization for current-mode logic with transformer

• US 9,853,842 B2
• Filed: 11/22/2016
• Issued: 12/26/2017
• Est. Priority Date: 04/06/2015
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Inphi Corporation
• Inventors: Mishra, Parmanand, Nielsen, Steffen, Harwood, Michael S.
• Primary Examiner(s): Flores, Leon
• Application Number:
  US15/359,338
• Publication Number:
  US 20170078120A1
• Time in Patent Office: 399 Days
• CPC Class Codes: H03K 19/094 using field-effect transistors
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

Claims

1. A communication system comprising:

a pair of differential input terminals, the pair of differential input terminals comprising a first input and a second input for receiving data;

a current mode logic device comprising;

a first transistor comprising a first gate and a first output terminal and a first source terminal, the first gate being electrically coupled to the first input;

a second transistor comprising a second gate and a second output terminal, the second gate being electrically coupled to the second input;

a capacitor module coupled to the first source terminal;

a first resistor coupled to the first output terminal;

a second resistor coupled to the second output terminal;

a first transformer comprising a first primary winding and a first secondary winding, the first primary winding being electrically coupled to the first resistor and the first output terminal; and

a first equalization module coupled to the first secondary winding, the first equalization module comprising a first digital-to-analog converter (DAC) unit, the DAC unit being configure to adjust an impedance value of the first equalization module in response to an equalization signal; and

a SerDes device being coupled to the first output terminal.

2. The system of claim 1 wherein the first equalization module further comprises a plurality of capacitors switched by the first DAC.

3. The system of claim 1 wherein the first equalization module further comprises a plurality of resistors switched by the first DAC.

4. The system of claim 1 further comprising a second transformer, the second transformer comprising a second primary winding and a second secondary winding.

5. The system of claim 4 further comprising a second equalization module coupled to the second secondary winding, wherein the second equalization module comprises a second DAC unit and a second plurality of resistors.

6. The system of claim 1 wherein the capacitor module comprises a second DAC unit and a plurality of capacitors, the plurality of capacitors being switched based on control signals of the second DAC unit.

7. The system of claim 1 wherein the first equalization module is coupled to a decision feedback equalization module.

8. The system of claim 1 wherein the first equalization module comprises a plurality of resistors and a plurality of capacitors.

9. A method for equalizing signals using a common-mode logic (CML) device, the method comprising:

receiving a pair of differential input signals using a pair of input transistors, the pair of input transistors including a first transistor, the first transistor including a first source terminal and a first drain terminal;

receiving a bias control signal;

configuring a capacitor module using at least the bias control signal, the capacitor module being coupled to the first source terminal;

receiving a first equalization signal;

adjusting a first peaking level of a first equalizer module using the first equalization signal;

adjusting a first inductance value of a first transformer using the first equalizer module, the first transformer being coupled to a first output load; and

generating a first output signal based at least on the different input signal and first inductance value of the first transformer, the first output signal being coupled to the first drain terminal.

10. The method of claim 9 further comprising generating the first equalization signal using a decision feedback equalization.

11. The method of claim 9 further comprising selectively switching a plurality of capacitors using the bias control signal, the capacitor module comprising the plurality of capacitors.

12. The method of claim 9 further comprising:

receiving a second equalization signal;

adjusting a second peak level of a second equalizer module using the second equalization signal;

adjusting a second inductance value of a second transformer using the second equalizer module.

13. The method of claim 9 further comprising selectively switch a plurality of resistors using the first equalization signal, the first equalizer module comprising the plurality of resistors.

14. The method of claim 9 further comprising selectively switch a plurality of capacitors using the first equalization signal, the first equalizer module comprising the plurality of capacitors.

15. The method of claim 9 further comprising converting the first equalization signal from a digital code to an analog signal using a DAC.

16. A method for equalizing signals using a common-mode logic (CML) device, the method comprising:

receiving a pair of differential input signals using a pair of input transistors, the pair of input transistors including a first transistor, the first transistor including a first source terminal and a first drain terminal;

receiving a bias control signal;

configuring a capacitor module using at least the bias control signal, the capacitor module being coupled to a first source terminal;

receiving the first equalization signal;

converting the equalization signal to a plurality of control bits using a DAC;

providing an equalization module, the equalization module comprising a plurality of resistors and being coupled to a transformer;

switching the plurality of resistors using the plurality of control bits;

generating a first output signal based at least on the different input signal and first inductance value of the transformer, the first output signal being coupled to the first drain terminal.

17. The method of claim 16 further comprising switching a plurality of capacitors using the plurality of control bits.

18. The method of claim 16 further comprising adjusting an inductance value of the transformer.

19. The method of claim 16 wherein the transformer is coupled to a load resistor.

20. The method of claim 16 further comprising converting the bias control signal to a plurality of control bits.