Sealed packaging for microelectromechanical systems

• US 9,856,132 B2
• Filed: 09/18/2011
• Issued: 01/02/2018
• Est. Priority Date: 09/18/2010
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Bryzek, Janusz, Bloomsburgh, John Gardner, Acar, Cenk
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): NGUYEN, LAWRENCE-LIN T
• Application Number:
  US13/821,589
• Publication Number:
  US 20130270660A1
• Time in Patent Office: 2,298 Days
• Field of Search: 257678-733, 257E23001-E23194, 257704, 257924, 257E23128, 257E2318-E23193, 257693, 257700-705, 257708-710, 257 37, 257774, 257E2132, 257E21561, 257E21564, 257E217, 257E21703
• CPC Class Codes: B81B 3/0021 Transducers for transforming electrical into mechanical energy or vice versa dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00
• CPC Class Codes: B81B 3/0072 For controlling internal stress or strain in moving or flexible elements, e.g. stress compensating layers
• CPC Class Codes: B81B 7/0016 Protection against shocks or vibrations, e.g. vibration damping
• CPC Class Codes: B81B 7/0051 between the package lid and the substrate
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: B81C 2203/0785 Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit, wherein the microelectromechanical layer includes a cap comprising a membrane that extends to the integrated circuit.

Claims

1. An apparatus, comprising:

a via wafer including a main portion and an elongate arm extending away from the main portion;

a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the via wafer using a central anchor, wherein the central anchor is configured to dispose the microelectromechanical layer away from the via wafer by a gap;

an application specific integrated circuit (ASIC) attached to the elongate arm of the via wafer using a solder interconnect; and

a cap, coupled to the via wafer, configured to enclose the microelectromechanical layer between the cap and the via wafer, wherein the elongate arm is configured to protect the microelectromechanical layer from deformation or stress.

2. The apparatus of claim 1, wherein the ASIC is coupled to a substrate using a cluster of electrical interconnects centrally disposed between the ASIC and the substrate.

3. The apparatus of claim 1, wherein the elongate arm is part of a plurality of elongate arms, wherein for each respective elongate arm on a side of the via wafer, there is an opposing elongate arm on an opposite side of the via wafer.

4. The apparatus of claim 1, comprising a solder ring disposed between the cap and the via wafer to define a hermetic seal between the via wafer and the microelectromechanical layer.

5. The apparatus of claim 1, wherein the microelectromechanical layer is disposed away from the cap by a gap.

6. The apparatus of claim 1, wherein the cap is coupled to the main portion of the via wafer.

7. The apparatus of claim 6, wherein the elongate arm is located outside of the cap.

8. The apparatus of claim 1, wherein the main portion of the via wafer is coplanar to the elongate arm of the via wafer.

9. The apparatus of claim 1, wherein the ASIC separates the microelectromechanical layer from the via wafer.

10. An apparatus, comprising:

a via wafer including a main portion and an elongate arm extending away from the main portion;

a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the via wafer using a central anchor, wherein the central anchor is configured to dispose the microelectromechanical layer away from the via wafer by a gap;

an application specific integrated circuit (ASIC) attached to the elongate arm of the via wafer using a solder interconnect; and

a cap, coupled to the via wafer, configured to enclose the microelectromechanical layer between the cap and the via wafer, wherein the elongate arm is configured to protect the microelectromechanical layer from deformation or stress,

wherein the elongate arm is part of a plurality of elongate arms, wherein for each respective elongate arm on a side of the via wafer, there is an opposing elongate arm on an opposite side of the via wafer.

11. The apparatus of claim 10, wherein the ASIC is coupled to a substrate using a cluster of electrical interconnects centrally disposed between the ASIC and the substrate.

12. The apparatus of claim 10, comprising a solder ring disposed between the cap and the via wafer to define a hermetic seal between the via wafer and the microelectromechanical layer.

13. The apparatus of claim 10, wherein the microelectromechanical layer is disposed away from the cap by a gap.

14. The apparatus of claim 10, wherein the cap is coupled to the main portion of the via wafer.

15. The apparatus of claim 14, wherein the elongate arm is located outside of the cap.

16. The apparatus of claim 10, wherein the main portion of the via wafer is coplanar to the elongate arm of the via wafer.

17. The apparatus of claim 10, wherein the ASIC separates the microelectromechanical layer from the via wafer.

18. An apparatus, comprising:

a via wafer including a main portion and an elongate arm extending away from the main portion;

a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the via wafer using a central anchor, wherein the central anchor is configured to dispose the microelectromechanical layer away from the via wafer by a gap;

an application specific integrated circuit (ASIC) attached to the elongate arm of the via wafer using a solder interconnect; and

a cap, coupled to the via wafer, configured to enclose the microelectromechanical layer between the cap and the via wafer, wherein the elongate arm is configured to protect the microelectromechanical layer from deformation or stress,

wherein the ASIC is coupled to a substrate using a cluster of electrical interconnects centrally disposed between the ASIC and the substrate.

19. The apparatus of claim 18, wherein the microelectromechanical layer is disposed away from the cap by a gap, and

wherein the cap is coupled to the main portion of the via wafer.

20. The apparatus of claim 18, wherein the elongate arm is part of a plurality of elongate arms, wherein for each respective elongate arm on a side of the via wafer, there is an opposing elongate arm on an opposite side of the via wafer, and

wherein the ASIC is coupled to a substrate using a cluster of electrical interconnects centrally disposed between the ASIC and the substrate.