Biasing for lower RON of LDO pass devices
First Claim
1. A circuital arrangement for biasing a cascoded transistor of a stack of transistors arranged in a cascode configuration, the circuital arrangement comprising:
- a stack of at least two transistors arranged in a cascode configuration, comprising an input transistor and a first cascoded transistor; and
a biasing circuit configured to provide a first bias voltage to the first cascoded transistor,wherein;
a supply voltage to the stack is a varying supply voltage, andthe first bias voltage is at a substantially constant offset voltage with respect to the varying supply voltage.
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Accused Products
Abstract
Systems, methods and apparatus for efficient control and biasing of pass devices driven into their triode region of operation are described. The pass devices are arranged in a cascode configuration comprising a plurality of stacked devices. Biasing of the cascode devices can be according to a voltage division scheme which provides a substantially equal voltage division across the stacked devices when the voltage across the stack is high, and provides a skewed voltage division across the stacked devices when voltage across the stack is reduced, while protecting each of the devices from overvoltage and biasing the cascoded devices for a low RON. An exemplary implementation of an LDO controlling the pass devices for providing burst RF power to a power amplifier is described.
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Citations
25 Claims
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1. A circuital arrangement for biasing a cascoded transistor of a stack of transistors arranged in a cascode configuration, the circuital arrangement comprising:
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a stack of at least two transistors arranged in a cascode configuration, comprising an input transistor and a first cascoded transistor; and a biasing circuit configured to provide a first bias voltage to the first cascoded transistor, wherein; a supply voltage to the stack is a varying supply voltage, and the first bias voltage is at a substantially constant offset voltage with respect to the varying supply voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method for biasing a stack of transistors, the method comprising:
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providing a stack of at least two transistors arranged in a cascode configuration, the stack comprising an input transistor and one or more cascoded transistors; supplying a supply voltage across the stack; biasing the one or more cascoded transistors with respective one or more biasing voltages, the respective one or more biasing voltages having each a substantially constant offset voltage with respect to the supply voltage; providing a control voltage to the input transistor; based on the providing of the control voltage, driving the input transistor in its triode region of operation; based on the driving, driving the one or more cascoded transistors in their respective triode regions of operation; based on the biasing, obtaining an ON resistance RON for each of the one or more cascoded transistors; varying the supply voltage; and based on the varying and the biasing, maintaining the ON resistance RON of the one or more cascoded transistors. - View Dependent Claims (21, 22, 23)
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24. A method for biasing a cascoded stack of transistors, the method comprising:
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applying a varying supply voltage across the stack; when the varying supply voltage is at a high voltage, biasing cascoded transistors of the stack for a substantially equal voltage division of the high voltage across all transistors of the stack; and when the varying supply voltage is below the high voltage, biasing the cascoded transistors for a skewed voltage division of the varying supply voltage across the all transistors of the stack. - View Dependent Claims (25)
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Specification