Host interface controller and control method for storage device

• US 9,857,981 B2
• Filed: 05/20/2016
• Issued: 01/02/2018
• Est. Priority Date: 12/09/2015
• Status: Active Grant

• Current Assignee: Via Alliance Semiconductor Co., Ltd.
• Original Assignee: Via Alliance Semiconductor Co., Ltd.
• Inventors: Li, Lin, Dong, Yunxing, Hui, Zhiqiang
• Primary Examiner(s): DUDEK JR, EDWARD J
• Application Number:
  US15/160,803
• Publication Number:
  US 20170168846A1
• Time in Patent Office: 592 Days
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Abstract

A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.

Claims

1. A host interface controller, coupled to a central processing unit, comprising:

a control module;

a first buffer set and a second buffer set, temporarily storing data read from a storage device to respond to read requests from the central processing unit; and

a buffer mode setting register, switched during a start-up procedure based on whether a cache memory of the central processing unit has started up or not,

wherein;

when the cache memory has not started up, the first buffer set and the second buffer set operate in a cache memory mode to respond to read requests that the central processing unit repeatedly issues for data of specific addresses of the storage device; and

when the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the central processing unit issues for data of sequential addresses of the storage device.

2. The host interface controller as claimed in claim 1, wherein:

when the first buffer set and the second buffer set operate in the cache memory mode, the control module reads the storage device in a data length of several line buffers of the first and second buffer sets and buffers the data read from the storage device in the data length into the first and the second buffer sets.

3. The host interface controller as claimed in claim 1, wherein:

when the first buffer set and the second buffer set operate in the ping-pong buffer mode, the control module alternately uses the first buffer set and the second buffer set as a pre-fetch buffer set;

when one of the first buffer set and the second buffer set works as the pre-fetch buffer set, the control module pre-fetches and buffers data starting from a first address of the storage device into the pre-fetch buffer set and accesses the other one of the first buffer set and the second buffer set to respond to a read request that the central processing unit issues to access data of a second address of the storage device.

4. The host interface controller as claimed in claim 1, wherein:

when the first buffer set and the second buffer set operate in the ping-pong buffer mode, a data length of the data read from the storage device is controlled by the control module itself.

5. The host interface controller as claimed in claim 1, further comprising:

a first register set, corresponding to the first buffer set and storing address information about data buffered in the first buffer set; and

a second register set, corresponding to the second buffer set and storing address information about data buffered in the second buffer set.

6. The host interface controller as claimed in claim 5, wherein:

the first register set stores high address bits of data buffered in the first buffer set;

the second register set stores high address bits of data buffered in the second buffer set; and

the first register set and the second register set form a table indexed by low address bits of the corresponding data stored in the first buffer set and the second buffer set.

7. The host interface controller as claimed in claim 5, further comprising:

a multiplexer, retrieving the first and second register sets according to a target index to output reference high address bits, wherein the target index is transformed from low address bits of a read address requested by the central processing unit; and

a comparator, comparing the reference high address bits with high address bits of the read address to determine whether the data of the read address of the storage device has been pre-fetched and buffered in the first or second buffer set,

wherein, when the data of the read address of the storage device has been pre-fetched and buffered in the first or second buffer set, the control module retrieves the first and second buffer sets according to the target index to provide data to respond to a read request of the read address issued from the central processing unit.

8. The host interface controller as claimed in claim 1, wherein:

when the first buffer set and the second buffer set operate in the cache memory mode and data of the storage device of a read address requested by the central processing unit has not been pre-fetched and buffered in the first and second buffer sets, the control module reads the storage device in a data length of several line buffers of the first and second buffer sets and buffers the data read from the storage device in the data length into the first and the second buffer sets.

9. The host interface controller as claimed in claim 1, wherein:

when the first buffer set and the second buffer set operate in the ping-pong buffer mode and a read address requested by the central processing unit is not sequential to a previous read address requested by the central processing unit and data of the storage device of the read address has not been pre-fetched and buffered in the first and second buffer sets, the control module reads the storage device for data with sequential addresses starting from the read address and uses the data read from the storage device with the sequential addresses starting from the read address to update the first and second buffer sets from a target index transformed from the read address to a last index of the first and second buffer sets.

10. The host interface controller as claimed in claim 1, wherein:

when the first buffer set and the second buffer set operate in the ping-pong buffer mode and a read address requested by the central processing unit is sequential to a previous read address requested by the central processing unit, the control module determines whether a target index transformed from the read address points to a first line buffer of the first buffer set or a first line buffer of the second buffer set;

when the target index points to the first line buffer of the first buffer set, the control module switches to operate the second buffer set as the pre-fetch buffer set; and

when the target index points to the first line buffer of the second buffer set, the control module switches to operate the first buffer set as the pre-fetch buffer set.

11. A control method for a storage device, comprising:

providing a first buffer set and a second buffer set within a host interface controller between a storage device and a central processing unit to temporarily store data read from the storage device to respond to read requests issued from the central processing unit;

when a cache memory of the central processing unit has not started up during a start-up procedure, operating the first buffer set and the second buffer set processing unit repeatedly issues for data of specific addresses of the storage device; and

when the cache memory of the central processing unit has started up during the start-up procedure, operating the first buffer set and the second buffer set in a ping-pong buffer mode to respond to read requests that the central processing unit issues for data of sequential addresses of the storage device.

12. The control method as claimed in claim 11, wherein:

when the first buffer set and the second buffer set operate in the cache memory mode, the storage device is read in a data length of several line buffers of the first and second buffer sets and the data read from the storage device is buffered in the data length into the first and the second buffer sets.

13. The control method as claimed in claim 11, wherein:

when the first buffer set and the second buffer set operate in the ping-pong buffer mode, the first buffer set and the second buffer set alternately work as a pre-fetch buffer set;

when one of the first buffer set and the second buffer set works as the pre-fetch buffer set, data starting from a first address of the storage device is pre-fetched and buffered into the pre-fetch buffer set and the other one of the first buffer set and the second buffer set is accessed to respond to a read request that the central processing unit issues to access data of a second address of the storage device.

14. The control method as claimed in claim 11, wherein:

when the first buffer set and the second buffer set operate in the ping-pong buffer mode, a data length of the data read from the storage device is controlled by the host interface controller itself.

15. The control method as claimed in claim 11, further comprising:

providing a first register set corresponding to the first buffer set and storing address information about data buffered in the first buffer set; and

providing a second register set corresponding to the second buffer set and storing address information about data buffered in the second buffer set.

16. The control method as claimed in claim 15, wherein:

the first register set stores high address bits of data buffered in the first buffer set;

the second register set stores high address bits of data buffered in the second buffer set; and

the first register set and the second register set form a table indexed by low address bits of the corresponding data stored in the first buffer set and the second buffer set.

17. The control method as claimed in claim 15, further comprising:

retrieving the first and second register sets according to a target index to output reference high address bits, wherein the target index is transformed from low address bits of a read address requested by the central processing unit;

comparing the reference high address bits with high address bits of the read address to determine whether the data of the read address of the storage device has been pre-fetched and buffered in the first or second buffer set; and

when the data of the read address of the storage device has been pre-fetched and buffered in the first or second buffer set, retrieving the first and second buffer sets according to the target index to provide data to respond to a read request of the read address issued from the central processing unit.

18. The control method as claimed in claim 11, further comprising:

when the first buffer set and the second buffer set operate in the cache memory mode and data of the storage device of a read address requested by the central processing unit has not been pre-fetched and buffered in the first and second buffer sets, reading the storage device in a data length of several line buffers of the first and second buffer sets and buffering the data read from the storage device in the data length into the first and the second buffer sets.

19. The control method as claimed in claim 11, further comprising:

when the first buffer set and the second buffer set operate in the ping-pong buffer mode and a read address requested by the central processing unit is not sequential to a previous read address requested by the central processing unit and data of the storage device of the read address has not been pre-fetched and buffered in the first and second buffer sets, reading the storage device for data with sequential addresses starting from the read address and using the data read from the storage device with the sequential addresses starting from the read address to update the first and second buffer sets from a target index transformed from the read address to a last index of the first and second buffer sets.

20. The control method as claimed in claim 11, further comprising:

when the first buffer set and the second buffer set operate in the ping-pong buffer mode and a read address requested by the central processing unit is sequential to a previous read address requested by the central processing unit, determining whether a target index transformed from the read address points to a first line buffer of the first buffer set or a first line buffer of the second buffer set;

when the target index points to the first line buffer of the first buffer set, switching to operate the second buffer set as the pre-fetch buffer set; and

when the target index points to the first line buffer of the second buffer set, switching to operate the first buffer set as the pre-fetch buffer set.