Hierarchical pre-fetch pipelining in a hybrid memory server

• US 9,857,987 B2
• Filed: 04/27/2016
• Issued: 01/02/2018
• Est. Priority Date: 06/24/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Yuk Lung, Krishnamurthy, Rajaram B., Parris, Carl Joseph
• Primary Examiner(s): BILGRAMI, ASGHAR H
• Application Number:
  US15/139,405
• Publication Number:
  US 20160239425A1
• Time in Patent Office: 615 Days
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 16/172 Caching, prefetching or hoarding of files
• CPC Class Codes: G06F 16/182 Distributed file systems
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 2212/264 Remote server
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: H04L 41/5054 Automatic deployment of services triggered by the service manager, e.g. service implementation by automatic configuration of network components
• CPC Class Codes: H04L 47/24 Traffic characterised by specific attributes, e.g. priority or QoS
• CPC Class Codes: H04L 67/568 Storing data temporarily at an intermediate stage, e.g. caching

Abstract

A method, hybrid server system, and computer program product, prefetch data. A set of prefetch requests associated with one or more given datasets residing on the server system are received from a set of accelerator systems. A set of data is prefetched from a memory system residing at the server system for at least one prefetch request in the set of prefetch requests. The set of data satisfies the at least one prefetch request. The set of data that has been prefetched is sent to at least one accelerator system, in the set of accelerator systems, associated with the at least one prefetch request.

Claims

1. A method, with a hybrid server system in an out-of-core processing environment, comprising:

partitioning a memory system partitioned into a first set of memory managed by a server, and a second set of memory managed by a set of accelerator systems, the second set of memory being directly writeable to by the set of accelerator systems, and wherein the memory system comprises heterogeneous memory types;

identifying a data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems; and

transforming the data set from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

2. The method of claim 1, wherein the transforming is based on at least one of an operation associated with the data set and a type of the at least one processing core of the at least one accelerator system.

3. The method of claim 1, wherein partitioning the memory system comprises:

releasing the second set of memory to the set of accelerator systems.

4. The method of claim 1, wherein at least one accelerator system in the set of accelerator systems comprises at least one gated memory, wherein the at least one accelerator system selectively allows the server to access the at least one gate memory.

5. The method of claim 1, wherein the memory system comprises at least one flash memory module, and wherein the at least one flash memory module is communicatively coupled to an input-output bus of the server, wherein a first accelerator system in the set of accelerator systems communicates at least one data set residing within the flash memory to a second accelerator system in the set of accelerator systems over the input-output bus of the server, and wherein the first and second accelerator systems have direct access to the at least one flash memory module.

6. The method of claim 5, wherein the at least one flash memory module comprises a network link configured to at least one of send and receive messages from at least the set of accelerators.

7. A hybrid server system in an out-of-core processing environment comprising:

a server comprising

a memory system partitioned into a first set of memory managed by the server, and a second set of memory managed by a set of accelerator systems, the second set of memory being directly writeable to by the set of accelerator systems, and wherein the memory system comprises heterogeneous memory types;

a data access manager communicatively coupled to the memory system; and

a set of accelerator systems communicatively coupled to the server, wherein each accelerator system in the set of accelerator systems comprises at least one processing core,

wherein the data access manager is configured to

identify a data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems; and

transform the data set from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

8. The hybrid server system of claim 7, wherein the transforming is based on at least one of an operation associated with the data set and a type of the at least one processing core of the at least one accelerator system.

9. The hybrid server system of claim 7, wherein partitioning the memory system comprises:

releasing the second set of memory to the set of accelerator systems.

10. The hybrid server system of claim 7, wherein at least one accelerator system in the set of accelerator systems comprises at least one gated memory, wherein the at least one accelerator system selectively allows the server to access the at least one gate memory.

11. The hybrid server system of claim 7, wherein the memory system comprises at least one flash memory module, and wherein the at least one flash memory module is communicatively coupled to an input-output bus of the server, wherein a first accelerator system in the set of accelerator systems communicates at least one data set residing within the flash memory to a second accelerator system in the set of accelerator systems over the input-output bus of the server, and wherein the first and second accelerator systems have direct access to the at least one flash memory module.

12. The hybrid server system of claim 11, wherein the at least one flash memory module comprises a network link configured to at least one of send and receive messages from at least the set of accelerators.

13. A computer program product for managing data access in an out-of-core processing environment, the computer program product comprising:

a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

partitioning a memory system partitioned into a first set of memory managed by a server, and a second set of memory managed by a set of accelerator systems, the second set of memory being directly writeable to by the set of accelerator systems, and wherein the memory system comprises heterogeneous memory types;

identifying a data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems; and

transforming the data set from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

14. The computer program product of claim 13, wherein the transforming is based on at least one of an operation associated with the data set and a type of the at least one processing core of the at least one accelerator system.

15. The computer program product of claim 13, wherein partitioning the memory system comprises:

releasing the second set of memory to the set of accelerator systems.

16. The computer program product of claim 13, wherein at least one accelerator system in the set of accelerator systems comprises at least one gated memory, wherein the at least one accelerator system selectively allows the server to access the at least one gate memory.

17. The computer program product of claim 13, wherein the memory system comprises at least one flash memory module, and wherein the at least one flash memory module is communicatively coupled to an input-output bus of the server, wherein a first accelerator system in the set of accelerator systems communicates at least one data set residing within the flash memory to a second accelerator system in the set of accelerator systems over the input-output bus of the server, and wherein the first and second accelerator systems have direct access to the at least one flash memory module.

18. The computer program product of claim 17, wherein the at least one flash memory module comprises a network link configured to at least one of send and receive messages from at least the set of accelerators.