Copying of power-on reset sequencer descriptor from nonvolatile memory to random access memory

• US 9,858,084 B2
• Filed: 03/17/2014
• Issued: 01/02/2018
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Manlapat, Alvin Anonuevo, Beleno, Ian Victor Pasion
• Primary Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US14/217,399
• Publication Number:
  US 20140331034A1
• Time in Patent Office: 1,387 Days
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A mechanism of booting up a system directly from a storage device and a means of initializing an embedded system prior to activating a CPU is presented. The said system is comprised of one or more CPUs, a reset controller, a storage device controller, one or more direct memory access controllers, a RAM and its controller, a ROM and its controller, a debug interface and a power-on reset (POR) sequencer. The POR sequencer controls the overall boot process of the embedded system. Said sequencer uses descriptors (POR Sequencer descriptors) which are used to update the configuration registers of the system and to enable CPU-independent data transfers with the use of DMA controllers.

Using a minimal amount of non-volatile memory for booting up a system brings down costs associated with increased silicon real estate area and power consumption. Capability of pre-initializing the system even before a CPU is brought out of reset provides flexibility and system robustness. Through the use of the Power-On Reset Sequencer module, integrity of program code and user data used in the boot up process can be verified thus providing a resilient boot up sequence.

Claims

1. A computer-implemented method, comprising:

releasing components of an embedded system from reset;

detecting a power-on reset (POR) sequencer descriptor in a nonvolatile memory;

wherein the POR sequencer descriptor comprises information to initialize configuration registers of the embedded system, Direct Memory Access (DMA) descriptors used to fetch other POR sequencer descriptor fragments, and a system firmware;

copying the POR sequencer descriptor from the nonvolatile memory to a random access memory (RAM);

verifying an integrity of the POR sequencer descriptor; and

detecting any error in the POR sequencer descriptor;

wherein the computer-implemented method allows the embedded system to verify an integrity of user data and program code used in a boot process in order to provide a resilient boot up sequence and wherein the computer-implemented method reduces an amount of the nonvolatile memory used in the boot process.

2. The method of claim 1, further comprising:

if a copy of the POR sequencer descriptor is not detected in the nonvolatile memory, then detecting a second copy of the POR sequencer descriptor and copying the second copy from the nonvolatile memory to the RAM.

3. The method of claim 1, further comprising:

if a copy of the POR sequencer descriptor is not successfully detected, then updating the nonvolatile memory with a new POR sequencer descriptor.

4. The method of claim 1, wherein verifying the integrity comprises comparing a computed checksum to a checksum of the POR sequencer descriptor.

5. The method of claim 1, further comprising

activating a POR sequencer error handler if an error is detected in the POR sequencer descriptor.

6. The method of claim 1, wherein the components comprises a processor bus, a reset controller, a direct memory access (DMA) controller, a storage device controller, a RAM controller, nonvolatile memory controller, and a POR sequencer.

7. The method of claim 1, further comprising:

stabilizing an input power supply to the embedded system after power-up.

8. The method of claim 1, further comprising:

performing a register initialization phase in the embedded system.

9. The method of claim 1, further comprising:

copying system firmware from a storage device to the RAM.

10. An apparatus, comprising:

an embedded system configured to release components of the embedded system from reset;

wherein the embedded system comprises a power-on reset (POR) sequencer configured to detect a (POR) sequencer descriptor in a nonvolatile memory, to copy the POR sequencer descriptor from the nonvolatile memory to a random access memory (RAM), to verify an integrity of the POR sequencer descriptor, and to detect any error in the POR sequencer descriptor;

wherein the POR sequencer descriptor comprises information to initialize configuration registers of the embedded system, Direct Memory Access (DMA) descriptors used to fetch other POR sequencer descriptor fragments, and a system firmware;

wherein the POR sequencer comprises a bus master interface that manages data and control signals to and from a Central Processor Unit (CPU) bus, a memory controller port interface that manages control signals to and from the RAM, and a POR sequencer state machine that utilizes the bus master interface to perform data transfer to and from the CPU bus and utilizes the memory controller port interface to perform data transfer to and from the RAM.

11. The apparatus of claim 10, wherein if a copy of the POR sequencer descriptor is not detected in the nonvolatile memory, then the POR sequencer is configured to detect a second copy of the POR sequencer descriptor and to copy the second copy from the nonvolatile memory to the RAM.

12. The apparatus of claim 10, wherein if a copy of the POR sequencer descriptor is not successfully detected, then a system integrator is configured to update the nonvolatile memory with a new POR sequencer descriptor.

13. The apparatus of claim 10, wherein the POR sequencer is configured to verify the integrity by comparing a computed checksum to a checksum of the POR sequencer descriptor.

14. The apparatus of claim 10, wherein a POR sequencer error handler is activated if an error is detected in the POR sequencer descriptor.

15. The apparatus of claim 10, wherein the components comprises a processor bus, a reset controller, a direct memory access (DMA) controller, a storage device controller, a RAM controller, nonvolatile memory controller, and a POR sequencer.

16. The apparatus of claim 10, wherein an input power supply to the embedded system is stabilized after power-up.

17. The apparatus of claim 10, wherein the POR sequencer is configured to perform a register initialization phase in the embedded system.

18. The apparatus of claim 10, wherein the embedded system is configured to copy system firmware from a storage device to the RAM.

19. An article of manufacture, comprising:

a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising;

releasing components of an embedded system from reset;

detecting a power-on reset (POR) sequencer descriptor in a nonvolatile memory;

wherein the POR sequencer descriptor comprises information to initialize configuration registers of the embedded system, Direct Memory Access (DMA) descriptors used to fetch other POR sequencer descriptor fragments, and a system firmware;

copying the POR sequencer descriptor from the nonvolatile memory to a random access memory;

verifying an integrity of the POR sequencer descriptor; and

detecting any error in the POR sequencer descriptor.

20. The article of manufacture of claim 19, wherein the instructions are further operable to permit the apparatus to activate a POR sequencer error handler if an error is detected in the POR sequencer descriptor.