Storage controller and method for managing a solid-state memory

• US 9,858,289 B2
• Filed: 11/05/2015
• Issued: 01/02/2018
• Est. Priority Date: 11/05/2015
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ioannou, Nikolas
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US14/933,770
• Publication Number:
  US 20170132245A1
• Time in Patent Office: 789 Days
• Field of Search: 711103
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 16/178 Techniques for file synchronisation in file systems
• CPC Class Codes: G06F 16/1847 specifically adapted to static storage, e.g. adapted to flash memory or SSD
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control

Abstract

A storage controller for managing a solid-state memory is suggested. The solid-state memory includes a plurality of physical addresses. The storage controller comprises a mapping table for mapping a plurality of logical addresses to the plurality of physical addresses, the mapping table including mapping values, each mapping value defining the mapping of one logical address to one physical address, a processing unit for performing linearizable operations on the mapping values, the processing unit configured to concurrently execute some of the linearizable operations, a synchronization unit for mediating the concurrently executed linearizable operations, the synchronization unit configured to examine a mapping value of the mapping table, compare the examined mapping value with a known mapping value, the known mapping value being the last known value for the examined mapping value, and, if the examined mapping value and the known mapping value are identical, update the examined mapping value with a new mapping value.

Claims

1. A storage controller for managing a solid-state memory, the solid-state memory including a plurality of physical addresses, the storage controller comprising:

a mapping table for mapping a plurality of logical addresses to the plurality of physical addresses, the mapping table including mapping values, each mapping value defining the mapping of one logical address to one physical address;

a processing unit for performing linearizable operations on the mapping values, the processing unit configured to concurrently execute at least some of the linearizable operations; and

a synchronization unit for mediating the concurrently executed linearizable operations, the synchronization unit configured to examine a mapping value of the mapping table, to compare the examined mapping value with a known mapping value, the known mapping value being the last known value for the examined mapping value, and, when the examined mapping value and the known mapping value are identical, to update the examined mapping value with a new mapping value;

wherein, when the processing unit performs an unaligned write request to a logical address, the synchronization unit is configured to determine a mapping value corresponding to the logical address of the write request as a known mapping value, to determine the current physical address from the known mapping value and wherein the processing unit is configured to read the data from the current physical address and to store the read data in a buffer.

2. The storage controller of claim 1, wherein the linearizable operations include at least one of a read operation, a write operation and a relocate operation.

3. The storage controller of claim 1, wherein data is stored in the solid-state memory in a log-structured file system.

4. The storage controller of claim 1, wherein, when the processing unit performs a read request, the synchronization unit is configured to determine a logical address of the read request, to determine a corresponding physical address from the mapping table, and to determine whether the corresponding physical address is valid.

5. The storage controller of claim 4, wherein, when the corresponding physical address is valid, the processing unit is configured to perform the read request by reading the data of the physical address into a buffer.

6. The storage controller of claim 4, wherein, when the corresponding physical address is invalid, the processing unit is configured to perform the read request by filling a buffer with zero bits.

7. The storage controller of claim 1, wherein, when the processing unit performs an aligned write request to a logical address, the processing unit is configured to acquire an available physical address and to write data to the acquired physical address, and wherein the synchronization unit is configured to determine a mapping value corresponding to the logical address of the write request as a known mapping value, to determine the current physical address from the known mapping value, and to update the current physical address with the acquired physical address.

8. The storage controller of claim 7, wherein the synchronization unit is configured to determine whether the update was successful by examining a mapping value corresponding to the logical address, to compare the examined mapping value and the known mapping value and to decide that the update was successful when the examined mapping value and the known mapping value are identical.

9. The storage controller of claim 8, wherein the synchronization unit is configured to unmap the current physical address if the update was successful.

10. The storage controller of claim 9, wherein the synchronization unit is configured to determine a mapping value corresponding to the logical address of the write request as an examined mapping value and to compare the known mapping value and the examined mapping value.

11. The storage controller of claim 1, wherein the processing unit is configured to merge the data of the write request with the data stored in the buffer, to acquire an available physical address and to write the merged data to the acquired physical address.

12. The storage controller of claim 11, wherein the synchronization unit is configured to update the mapping value with the acquired physical address.

13. The storage controller of claim 12, wherein the synchronization unit is configured to determine whether the update was successful by examining a mapping value corresponding to the logical address, to compare the examined mapping value and the known mapping value and to decide that the update was successful when the examined mapping value and the known mapping value are identical.

14. The storage controller of claim 13, wherein the synchronization unit is configured to unmap the acquired physical address if the update was not successful and to unmap the current physical address if the update was successful.

15. The storage controller of claim 1, wherein, when the processing unit performs a relocate request of a physical address during a garbage collection operation, the synchronization unit is configured to determine the logical address corresponding to the physical address, to examine the mapping table and to determine a mapping value corresponding to the logical address as the known mapping value, and wherein the processing unit is configured to read the data from the physical address and to store the read data in a buffer.

16. The storage controller of claim 15, wherein the processing unit is configured to acquire an available physical address and to write the read data to the acquired physical address, and wherein the synchronization unit is configured to update the mapping value with the acquired physical address.

17. A storage controller for managing a solid-state memory, the solid-state memory including a plurality of physical addresses, the storage controller comprising:

a mapping table for mapping a plurality of logical addresses to the plurality of physical addresses, the mapping table including mapping values, each mapping value defining the mapping of one logical address to one physical address;

a processing unit for performing linearizable operations on the mapping values, the processing unit configured to concurrently execute at least some of the linearizable operations; and

a synchronization unit for mediating the concurrently executed linearizable operations, the synchronization unit configured to examine a mapping value of the mapping table, to compare the examined mapping value with a known mapping value, the known mapping value being the last known value for the examined mapping value, and, when the examined mapping value and the known mapping value are identical, to update the examined mapping value with a new mapping value;

wherein the processing unit is configured to acquire an available physical address and to write the read data to the acquired physical address, and wherein the synchronization unit is configured to update the mapping value with the acquired physical address; and

wherein the synchronization unit is configured to determine whether the update was successful by examining a mapping value corresponding to the logical address, to compare the examined mapping value and the known mapping value and to decide that the update was successful when the examined mapping value and the known mapping value are identical.

18. The storage controller of claim 17, wherein the synchronization unit is configured to unmap the acquired physical address if the update was not successful and to unmap the current physical address if the update was successful.

19. A method for managing a solid-state memory, the solid-state memory including a plurality of physical addresses, the method comprising:

mapping logical addresses to the plurality of physical addresses and storing the mapping in a mapping table, the mapping table including mapping values, each mapping value defining the mapping of one logical address to one physical address;

concurrently executing at least some linearizable operations on the mapping values, the linearizable operations including at least read and write operations;

mediating the concurrently executed linearizable operations by examining a mapping value of the mapping table, comparing the examined mapping value to a given mapping value, the given mapping value being the last known value for the examined mapping value, and, when the examined mapping value and the given mapping value are identical, updating the examined mapping value with a new mapping value; and

when performing an unaligned write request to a logical address, determining a mapping value corresponding to the logical address of the write request as a known mapping value, determining the current physical address from the known mapping value, and reading the data from the current physical address and storing the read data in a buffer.