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Method of analog front end optimization in presence of circuit nonlinearity

  • US 9,858,381 B2
  • Filed: 10/30/2015
  • Issued: 01/02/2018
  • Est. Priority Date: 12/02/2014
  • Status: Active Grant
First Claim
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1. A method for manufacturing a serial link comprising a channel and a receiver, the link comprising a plurality of linear time-invariant blocks, the receiver comprising a continuous-time linear equalizer (CTLE) comprising a nonlinear block having an input and an output, and a slicer having an input, the method comprising:

  • for one candidate CTLE configuration at a time of each of a plurality of candidate CTLE configurations of the CTLE;

    calculating a first input probability density function (PDF), corresponding to a first signal value, at the input of the nonlinear block;

    calculating a first output PDF, corresponding to the first signal value, at the output of the nonlinear block from the first PDF at the input of the nonlinear block;

    calculating a second input PDF, corresponding to a second signal value, at the input of the nonlinear block;

    calculating a second output PDF, corresponding to the second signal value, at the output of the nonlinear block from the second PDF at the input of the nonlinear block; and

    calculating a bit error rate, from;

    the first output PDF at the output of the nonlinear block; and

    the second output PDF at the output of the nonlinear block;

    selecting a configuration, from among the candidate CTLE configurations, satisfying a criterion related to the calculated bit error rate; and

    fabricating the CTLE with the selected configuration, utilizing integrated circuit fabrication equipment.

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