Method of analog front end optimization in presence of circuit nonlinearity
First Claim
1. A method for manufacturing a serial link comprising a channel and a receiver, the link comprising a plurality of linear time-invariant blocks, the receiver comprising a continuous-time linear equalizer (CTLE) comprising a nonlinear block having an input and an output, and a slicer having an input, the method comprising:
- for one candidate CTLE configuration at a time of each of a plurality of candidate CTLE configurations of the CTLE;
calculating a first input probability density function (PDF), corresponding to a first signal value, at the input of the nonlinear block;
calculating a first output PDF, corresponding to the first signal value, at the output of the nonlinear block from the first PDF at the input of the nonlinear block;
calculating a second input PDF, corresponding to a second signal value, at the input of the nonlinear block;
calculating a second output PDF, corresponding to the second signal value, at the output of the nonlinear block from the second PDF at the input of the nonlinear block; and
calculating a bit error rate, from;
the first output PDF at the output of the nonlinear block; and
the second output PDF at the output of the nonlinear block;
selecting a configuration, from among the candidate CTLE configurations, satisfying a criterion related to the calculated bit error rate; and
fabricating the CTLE with the selected configuration, utilizing integrated circuit fabrication equipment.
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Abstract
A method for manufacturing a serial link including a channel and a receiver, the link including linear time-invariant elements, the receiver including a continuous-time linear equalizer (CTLE) including a nonlinear block, and a slicer having an input. The method includes: for each of a plurality of candidate CTLE configurations: calculating a first probability density function (PDF), corresponding to a first signal value, at the input of the nonlinear block, calculating a first PDF, corresponding to the first signal value, at the output of the nonlinear block; calculating a second PDF, corresponding to a second signal value, at the input of the nonlinear block, calculating a second PDF, corresponding to the second signal value, at the output of the nonlinear block; and calculating a bit error rate.
21 Citations
20 Claims
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1. A method for manufacturing a serial link comprising a channel and a receiver, the link comprising a plurality of linear time-invariant blocks, the receiver comprising a continuous-time linear equalizer (CTLE) comprising a nonlinear block having an input and an output, and a slicer having an input, the method comprising:
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for one candidate CTLE configuration at a time of each of a plurality of candidate CTLE configurations of the CTLE; calculating a first input probability density function (PDF), corresponding to a first signal value, at the input of the nonlinear block; calculating a first output PDF, corresponding to the first signal value, at the output of the nonlinear block from the first PDF at the input of the nonlinear block; calculating a second input PDF, corresponding to a second signal value, at the input of the nonlinear block; calculating a second output PDF, corresponding to the second signal value, at the output of the nonlinear block from the second PDF at the input of the nonlinear block; and calculating a bit error rate, from; the first output PDF at the output of the nonlinear block; and the second output PDF at the output of the nonlinear block; selecting a configuration, from among the candidate CTLE configurations, satisfying a criterion related to the calculated bit error rate; and fabricating the CTLE with the selected configuration, utilizing integrated circuit fabrication equipment. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A system for manufacturing a serial data link comprising a channel and a receiver, the link comprising a plurality of linear time-invariant elements, the receiver having a continuous-time linear equalizer (CTLE) comprising a nonlinear block and a slicer having an input, the system comprising:
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a processing unit; and an integrated circuit fabrication equipment, the processing unit being configured to; for one candidate CTLE configuration at a time of each of a plurality of candidate CTLE configurations of the CTLE; calculate a first input probability density function (PDF), corresponding to a first signal value, at the input of the nonlinear block, calculate a first output PDF, corresponding to the first signal value, at the output of the nonlinear block from the first PDF at the input of the nonlinear block; calculate a second input PDF, corresponding to a second signal value, at the input of the nonlinear block, calculate a second output PDF, corresponding to the second signal value, at the output of the nonlinear block from the second PDF at the input of the nonlinear block; calculate a bit error rate, from; the first output PDF at the output of the nonlinear block; and the second output PDF at the output of the nonlinear block; select a configuration, from among the plurality of candidate CTLE configurations, satisfying a criterion; and the integrated circuit fabrication equipment being configured to fabricate the CTLE with the selected CTLE configuration. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A system for fabricating a serial data link comprising a channel and a receiver, the link comprising linear time-invariant elements, the receiver having a continuous-time linear equalizer (CTLE) comprising a nonlinear block and a slicer having an input, the system comprising:
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means for; for one candidate CTLE configuration at a time of each of a plurality of candidate CTLE configurations; calculating a first input probability density function (PDF), corresponding to a first signal value, at the input of the nonlinear block, calculating a first output probability density function (PDF), corresponding to the first signal value, at the output of the nonlinear block; calculating a second input probability density function (PDF), corresponding to a second signal value, at the input of the nonlinear block, calculating a second output probability density function (PDF), corresponding to the second signal value, at the output of the nonlinear block; calculating a bit error rate, from; the first output probability density function (PDF) at the output of the nonlinear block; and the second output probability density function (PDF) at the output of the nonlinear block; means for selecting a configuration, from among the configurations, satisfying a criterion; and integrated circuit fabrication equipment for fabricating a CTLE with the selected configuration.
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Specification