Nonvolatile RAM comprising a write circuit and a read circuit operating in parallel

• US 9,858,976 B2
• Filed: 09/15/2016
• Issued: 01/02/2018
• Est. Priority Date: 03/16/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ikegami, Kazutaka, Noguchi, Hiroki
• Primary Examiner(s): Graham, Kretelia
• Application Number:
  US15/266,327
• Publication Number:
  US 20170270988A1
• Time in Patent Office: 474 Days
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 15/02 using magnetic elements
• CPC Class Codes: G11C 2207/2209 Concurrent read and write for multi-port memory G11C7/1075
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

According to one embodiment, a nonvolatile RAM includes a memory cell array, a first circuit being allowed to access the memory cell array in a write operation using a first pulse, and a second circuit being allowed to access the memory cell array in a read operation using a second pulse, the second circuit being allowed to operate in parallel with an operation of the first circuit. A width of the first pulse is longer than a width of the second pulse.

Claims

1. A nonvolatile RAM comprising:

a memory cell array;

a first circuit being allowed to access the memory cell array in a write operation using a first pulse;

a second circuit being allowed to access the memory cell array in a read operation using a second pulse, the second circuit being allowed to operate in parallel with an operation of the first circuit; and

a write circuit selectively outputting one of a third pulse and a fourth pulse as the first pulse on the basis of a select signal,

wherein a width of the first pulse is longer than a width of the second pulse.

2. The nonvolatile RAM of claim 1, further comprising

an interface portion including a write buffer storing a write address and write data in the write operation, and being capable of outputting the write data in the write buffer as read data.

3. The nonvolatile RAM of claim 2, wherein the interface portion includes an address processing portion outputting a signal showing that a read address is coincident with the write address in the write buffer in the read operation.

4. The nonvolatile RAM of claim 3, wherein the address processing portion inhibits access to the memory cell array using the second circuit on the basis of the signal.

5. The nonvolatile RAM of claim 3, wherein the write buffer outputs the write data as the read data on the basis of the signal in the read operation.

6. The nonvolatile RAM of claim 5, wherein the write buffer is a content addressable memory.

7. The nonvolatile RAM of claim 5, wherein the interface portion includes a selector selectively outputting read data from the memory cell array or the read data from the write buffer.

8. The nonvolatile RAM of claim 2, wherein the interface portion includes an address processing portion outputting a signal showing that a read address is different from the write address in the write buffer in the read operation.

9. The nonvolatile RAM of claim 8, wherein the address processing portion allows access to the memory cell array using the second circuit on the basis of the signal.

10. The nonvolatile RAM of claim 9, further comprising

a read circuit reading the read data from the memory cell array.

11. The nonvolatile RAM of claim 10, wherein the interface portion includes a selector selectively outputting the read data from the read circuit or the read data from the write buffer.

12. The nonvolatile RAM of claim 1, wherein the memory cell array comprises:

blocks;

a first word line common to the blocks;

second word lines corresponding to the blocks; and

decoders electrically connected between the first word line and the second word lines.

13. The nonvolatile RAM of claim 1, wherein the first and second circuits do not operate in parallel, when a first memory cell in the memory cell array to be accessed by the first circuit and a second memory cell in the memory cell array to be accessed by the second circuit are disposed in the same row and are not the same memory cell.

14. The nonvolatile RAM of claim 13, wherein

access to the first memory cell using the first circuit is inhibited and

access to the second memory cell using the second circuit is allowed, when the first and second memory cells are disposed in the same row and are not the same memory cell.

15. The nonvolatile RAM of claim 13, wherein access to the first memory cell using the first circuit is allowed and access to the second memory cell using the second circuit is inhibited, when the first and second memory cells are disposed in the same row and are not the same memory cell.

16. The nonvolatile RAM of claim 1, wherein the first and second circuits operate in parallel, when a first memory cell in the memory cell array to be accessed by the first circuit and a second memory cell in the memory cell array to be accessed by the second circuit are the same memory cell.

17. The nonvolatile RAM of claim 1, wherein the third pulse has a first voltage and a first width, and the fourth pulse has a second voltage lower than the first voltage and a second width longer than the first width.

18. The nonvolatile RAM of claim 1, further comprising

a command processing portion outputting the select signal on the basis of a command in the write operation.

19. A system comprising:

the nonvolatile RAM of claim 18; and

a control portion controlling the nonvolatile RAM,

wherein the control portion issues the command on the basis of whether a speedup is required of the nonvolatile RAM.