Integrated circuit device including vertical memory device and method of manufacturing the same

• US 9,859,207 B2
• Filed: 08/24/2016
• Issued: 01/02/2018
• Est. Priority Date: 01/28/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Kwang-Soo
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US15/245,441
• Publication Number:
  US 20170221813A1
• Time in Patent Office: 496 Days
• Field of Search: 257774, 257324, 257326, 257773
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.

Claims

1. An integrated circuit (IC) device comprising:

a plurality of word lines that extend on a substrate parallel to a main surface of the substrate and are separated from one another in a first direction perpendicular to the main surface;

a channel region that extends in a first region on the substrate through the plurality of word lines;

a bit line contact pad that is on the channel region and contacts an upper surface of the channel region;

a bit line that contacts the bit line contact pad in the first region and extends on the bit line contact pad in a second direction parallel to the main surface of the substrate;

a common source line that partially fills a word line cut region in the first region and a second region separated from the first region, with a word line cut region buried insulating layer interposed between the common source line and the bit line in the first region, the word line cut region extending in a third direction on a side of the plurality of word lines, the third direction being parallel to the main surface of the substrate and intersecting the second direction, the common source line having a height from the substrate lower than that of the channel region; and

a common source via contact that contacts an upper surface of the common source line in the word line cut region in the second region and extends from the upper surface of the common source line in a direction away from the substrate.

2. The IC device of claim 1, wherein the common source line has a linear shape extending in the third direction in the word line cut region, and

the common source via contact has a plug shape extending in the first direction in a local region on the upper surface of the common source line.

3. The IC device of claim 1, wherein the common source via contact protrudes outward from inside the word line cut region.

4. The IC device of claim 1, wherein a distance from the substrate to an upper surface of the common source via contact is greater than a distance from the substrate to an upper surface of the bit line contact pad.

5. The IC device of claim 1, wherein a distance from the substrate to an upper surface of the common source via contact is greater than a distance from the substrate to an upper surface of the bit line.

6. The IC device of claim 1, wherein the word line cut region buried insulating layer covers the common source line in the word line cut region in the second region, and

the common source via contact is surrounded by the word line cut region buried insulating layer in the word line cut region.

7. The IC device of claim 1, wherein the IC device further comprises an insulating spacer between the common source line and the plurality of word lines, and the word line cut region buried insulating layer covers the common source line and the insulating spacer in the word line cut region, and

a width of the word line cut region buried insulating layer in the second direction is greater than a width of the common source line in the second direction.

8. The IC device of claim 1, wherein the IC device further comprises a dummy channel region that extends in the first direction through the plurality of word lines in the second region on the substrate, and

a dummy contact pad that is on the dummy channel region and contacts an upper surface of the dummy channel region.

9. The IC device of claim 8, wherein the dummy channel region comprises a material the same as that of the channel region, and the dummy contact pad comprises a material the same as that of the bit line contact pad.

10. The IC device of claim 8, wherein the common source line extends to pass the first region and the second region, and

the common source via contact is formed only in the second region from among the first region and the second region.

11. The IC device of claim 1, wherein the height of the common source line is less than two thirds (⅔

) of a total height of the word line cut region.

12. The IC device of claim 1, wherein the IC device further comprises:

at least one string select line that extends on the plurality of word lines, parallel to the plurality of word lines; and

the channel region that extends through the plurality of word lines and the at least one string select line,

wherein a level of an upper surface of the common source line is higher than a level of an upper surface of one of the at least one string select line that is farthest from the substrate.

13. The IC device of claim 1, wherein the IC device further comprises:

at least one string select line that extends on the plurality of word lines, parallel to the plurality of word lines; and

the channel region that extends through the plurality of word lines and the at least one string select line,

wherein a level of an upper surface of the common source line is lower than a level of a lower surface of one of the at least one string select line that is closest to the substrate.

14. The IC device of claim 1, wherein the IC device further comprises:

an insulating spacer between the common source line and the plurality of word lines; and

a word line cut region buried insulating layer that covers the common source line and the insulating spacer in the word line cut region,

wherein the word line cut region buried insulating layer includes a multilayer structure including at least two insulating layers of different materials.

15. The IC device of claim 1, wherein the IC device further comprises:

a first upper wiring layer on the bit line in the first region; and

a second upper wiring layer that is at a level the same as that of the first upper wiring layer in the second region and is connected to the common source via contact.