Cooling channels in 3DIC stacks

• US 9,859,252 B2
• Filed: 05/27/2016
• Issued: 01/02/2018
• Est. Priority Date: 11/13/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kai-Ming, Hsiao, Ching-Wen, Wang, Tsung-Ding, Tseng, Ming Hung, Chen, Chen-Shien
• Primary Examiner(s): Luu, Chuong A
• Application Number:
  US15/166,674
• Publication Number:
  US 20160276314A1
• Time in Patent Office: 585 Days
• Field of Search: 257737
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/46 involving the transfer of heat by flowing fluids H01L23/42, H01L23/44 take precedence
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

An integrated circuit structure includes a die including a semiconductor substrate, dielectric layers over the semiconductor substrate, an interconnect structure including metal lines and vias in the dielectric layers, a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers, and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

Claims

1. An integrated circuit structure comprising:

a first die comprising;

a semiconductor substrate;

a dielectric pipe penetrating through the semiconductor substrate;

a first portion of a fluidic channel in the dielectric pipe;

an interconnect structure comprising;

a plurality of dielectric layers; and

a plurality of metal layers in the plurality of dielectric layers, wherein portions of the plurality of metal layers define a second portion of the fluidic channel, and a space of the fluidic channel is separated from dielectric materials of the plurality of dielectric layers by metal features of the plurality of metal layers; and

two fluidic tubes connected to opposite ends of the fluidic channel.

2. The integrated circuit structure of claim 1 further comprising:

a dielectric film joined to the interconnect structure, with a space of the second portion of the fluidic channel exposed to the dielectric film; and

a first metal bump extending into the dielectric film.

3. The integrated circuit structure of claim 2, wherein the first metal bump penetrates through the dielectric film to be in physical contact with the interconnect structure.

4. The integrated circuit structure of claim 1, wherein the first die further comprises a first metal bump, and the integrated circuit structure further comprises:

a second die comprising a second metal bump bonded to the first metal bump; and

a third portion of the fluidic channel extending into the second die.

5. The integrated circuit structure of claim 4, wherein the second die comprises an additional semiconductor substrate, and the third portion of the fluidic channel extends to the additional semiconductor substrate.

6. The integrated circuit structure of claim 1, wherein the second portion of the fluidic channel comprises:

a portion aligned to the first portion of the fluidic channel; and

additional portions not aligned to the first portion of the fluidic channel.

7. The integrated circuit structure of claim 1, wherein the plurality of dielectric layers comprises a low-k dielectric material in contact with the metal features.

8. The integrated circuit structure of claim 1, wherein the dielectric pipe is in contact with the semiconductor substrate.

9. The integrated circuit structure of claim 1 further comprising an additional dielectric pipe penetrating through the semiconductor substrate, with a third portion of the fluid channel in the additional dielectric pipe.

18. The integrated circuit structure of claim 1 further comprising an additional dielectric pipe penetrating through the semiconductor substrate, with an additional portion of the fluidic channel in the additional dielectric pipe, wherein the first portion and the additional portion of the fluidic channel are connected to a same one of the two fluidic tubes.

20. The integrated circuit structure of claim 2, wherein the dielectric film comprises a photo resist, polyimide, or poly benzo oxysazole (PBO).

10. An integrated circuit structure comprising:

a first die comprising;

a semiconductor substrate;

an interconnect structure comprising a plurality of dielectric layers and a plurality of metal layers in the plurality of dielectric layers;

a fluidic channel comprising portions penetrating through both the semiconductor substrate and the interconnect structure, wherein the plurality of metal layers define a portion of a fluidic channel;

a dielectric film sealing the fluidic channel; and

a metal bump configured for bonding penetrating through the dielectric film to contact the interconnect structure.

11. The integrated circuit structure of claim 10, wherein the dielectric film comprises a photo sensitive polymer.

12. The integrated circuit structure of claim 10, wherein the metal bump comprises a solder.

13. The integrated circuit structure of claim 10 further comprising two fluidic tubes connected to opposite ends of the fluidic channel.

14. The integrated circuit structure of claim 10 further comprising:

a second die bonded to the first die, wherein the fluidic channel further extends into the second die.

15. The integrated circuit structure of claim 14, wherein the second die comprises an additional semiconductor substrate, and the additional semiconductor substrate is exposed to a space of the fluidic channel.

16. The integrated circuit structure of claim 10, wherein the metal bump comprises a surface coplanar with an end of the fluidic channel.

17. The integrated circuit structure of claim 10, wherein a portion of the fluidic channel in the semiconductor substrate is encircled by a dielectric pipe, and the dielectric pipe comprises an inner surface exposed to a space of the portion of the fluidic channel, and an outer surface in contact with the semiconductor substrate.

19. The integrated circuit structure of claim 13, wherein the fluidic channel comprises two portions penetrating through the semiconductor substrate, and the two portions are connected to a same one of the two fluidic tubes.