Silicon nitride fill for PC gap regions to increase cell density

• US 9,859,275 B2
• Filed: 01/26/2015
• Issued: 01/02/2018
• Est. Priority Date: 01/26/2015
• Status: Active Grant

• Current Assignee: Tessera LLC (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Guo, Dechao, Liu, Zuoguang, Yamashita, Tenko, Yeh, Chun-Chen
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US14/605,142
• Publication Number:
  US 20160218102A1
• Time in Patent Office: 1,072 Days
• Field of Search: 257365, 257369, 257390, 257E21616, 257E2706, 438 4, 438182, 438284, 438587
• CPC Class Codes: H01L 21/02134 the material comprising hydrogen silsesquioxane, e.g. HSQ
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence

Abstract

A semiconductor device is provided comprising a substrate, two or more semiconductor fins, and one or more gates. A flowable oxide layer is deposited on the semiconductor device. An area between the two or more semiconductor fins is etched such that the substrate is exposed. An insulating layer is deposited within the etched area. At least the flowable oxide layer is removed.

Claims

1. A semiconductor device comprising:

a substrate;

a first set of one or more semiconductor fins and a second set of one or more semiconductor fins formed on the substrate;

a first gate formed on the first set of one or more semiconductor fins and a second gate formed on the second set of one or more semiconductor fins;

an insulating layer formed on the substrate in an area between the first gate and the second gate; and

a third gate formed on the first set of one or more semiconductor fins and the second set of one or more semiconductor fins.

2. The semiconductor device of claim 1, further comprising:

a hard mask layer formed on the first gate and the second gate.

3. The semiconductor device of claim 1, wherein the area between the first gate and the second gate is less than or equal to ten nanometers.

4. The semiconductor device of claim 1, wherein the insulating layer is comprised of silicon nitride.

5. The semiconductor device of claim 1, wherein the first gate and the second gate are each comprised of polysilicon.

6. The semiconductor device of claim 1, wherein the first gate is electrically isolated from the second gate.

7. The semiconductor device of claim 1, wherein:

the first gate is nonadjacent to the second set of one or more semiconductor fins; and

the second gate is nonadjacent to the first set of one or more semiconductor fins.

8. The semiconductor device of claim 1, wherein:

the first set of one or more semiconductor fins comprises a first plurality of semiconductor fins; and

the second set of one or more semiconductor fins comprises a second plurality of semiconductor fins.