Semiconductor structure

• US 9,859,282 B1
• Filed: 09/29/2016
• Issued: 01/02/2018
• Est. Priority Date: 08/30/2016
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Tseng, Chun-Yen, Lung, Ching-Cheng, Kuo, Yu-Tse, Huang, Chun-Hsien, Wang, Shu-Ru
• Primary Examiner(s): Han, Jonathan
• Application Number:
  US15/280,333
• Time in Patent Office: 460 Days
• Field of Search: 257 68- 71, 257296-309, 257905-908, 257E27084-E27097, 257E27075, 257E21646-E2166
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A high-density semiconductor structure includes a substrate, a bit line and a first memory unit. The bit line, disposed on the substrate, has a first side and a second side. The first memory unit includes a first transistor, a first capacitor, a second transistor and a second capacitor. The first transistor disposed on the substrate has a first terminal and a second terminal. The first terminal connects the bit line. The first capacitor connects the second terminal of the first transistor. The second transistor disposed on the substrate has a third terminal and a fourth terminal. The third terminal connects the bit line. The second capacitor connects the fourth terminal of the second transistor. The first capacitor and the second capacitor are separated from the bit line in a direction perpendicular to an extending direction of the bit line and located on the first side of the bit line.

Claims

1. A semiconductor structure characterized in that the semiconductor structure comprises:

a substrate;

a bit line disposed on the substrate and having a first side and a second side opposite to the first side;

a first memory unit, comprising;

a first transistor disposed on the substrate and having a first terminal and a second terminal, wherein the first terminal connects to the bit line;

a first capacitor connecting to the second terminal of the first transistor;

a second transistor disposed on the substrate and having a third terminal and the fourth terminal, wherein the third terminal connects to the bit line; and

a second capacitor connecting to the fourth terminal of the second transistor;

wherein the first capacitor and the second capacitor are separated from the bit line in a direction perpendicular to an extending direction of the bit line, and the first capacitor and the second capacitor are located on the first side of the bit line; and

a second memory unit, comprising;

a third transistor disposed on the substrate and having a fifth terminal and a sixth terminal, wherein the fifth terminal connects to the bit line;

a third capacitor connecting to the sixth terminal of the third transistor;

a fourth transistor disposed on the substrate and having a seventh terminal and an eighth terminal, wherein the seventh terminal connects to the bit line; and

a fourth capacitor connecting to the eighth terminal of the fourth transistor;

wherein the third capacitor and the fourth capacitor are separated from the bit line in the direction perpendicular to the extending direction of the bit line, and the third capacitor and the fourth capacitor are located on the second side of the bit line.

2. The semiconductor structure according to claim 1, further comprising:

a first bit line contact disposed on the bit line;

wherein the first terminal of the first transistor and the third terminal of the second transistor are connected to the first bit line contact.

3. The semiconductor structure according to claim 2, wherein an active region of the first memory unit is divided into a first active region and a second active region, and the semiconductor structure further comprises:

a plurality of word lines extended in the direction perpendicular to the extending direction of the bit line, and comprising;

a first word line disposed on the first active region to define the first transistor; and

a second word line disposed on the second active region to define the second transistor.

4. The semiconductor structure according to claim 3, wherein an active region of the second memory unit is divided into a third active region and a fourth active region, and the plurality of word lines further comprise:

a third word line disposed on the third active region to define the third transistor; and

a fourth word line disposed on the fourth active region to define the fourth transistor.

5. The semiconductor structure according to claim 4, further comprising a plurality of memory units identical to the first memory unit and a plurality of memory units identical to the second memory unit, wherein the memory units identical to the first memory unit and the memory units identical to second memory unit are staggered with each other in the extending direction of the bit line.

6. The semiconductor structure according to claim 4, further comprising:

a second bit line contact disposed on the bit line;

wherein the fifth terminal of the third transistor and the seventh terminal of the fourth transistor are connected to the second bit line contact.

7. The semiconductor structure according to claim 6, wherein at least two of the plurality of word lines are located between the first bit line contact and the second bit line contact.

8. The semiconductor structure according to claim 5, wherein two of the capacitors of the memory units identical to the first memory unit and the memory units identical to the second memory unit that are disposed between adjacent two of the plurality word lines are respectively located on the first side and the second side of the bit line.