Three-dimensional resistive memory

• US 9,859,338 B2
• Filed: 03/21/2016
• Issued: 01/02/2018
• Est. Priority Date: 03/21/2016
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Chen, Frederick, Ho, Chia-Hua
• Primary Examiner(s): Parker, Allen
• Assistant Examiner(s): MUSE, ISMAIL A
• Application Number:
  US15/075,215
• Publication Number:
  US 20170271402A1
• Time in Patent Office: 652 Days
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/023 by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/883 Oxides or nitrides
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Provided is a three-dimensional resistive memory including a channel pillar, a first gate pillar, a first gate dielectric layer, first and second stacked structures, a variable resistance pillar and an electrode pillar. The channel pillar is on a substrate. The first gate pillar is on the substrate and at a first side of the channel pillar. The first gate dielectric layer is between the channel pillar and the first gate pillar. The first and second stacked structures are on the substrate and respectively at opposite second and third sides of the channel pillar. Each of the first and second stacked structures includes conductive material layers and insulating material layers alternately stacked. The variable resistance pillar is on the substrate and at a side of the first stacked structure opposite to the channel pillar. The electrode pillar is on the substrate and inside of the variable resistance pillar.

Claims

1. A three-dimensional resistive memory, comprising:

a channel pillar, disposed on a substrate;

a first gate pillar, disposed on the substrate and at a first side of the channel pillar;

a first gate dielectric layer, disposed between the channel pillar and the first gate pillar;

a first stacked structure and a second stacked structure, disposed on the substrate and respectively at opposite second and third sides of the channel pillar, wherein each of the first stacked structure and the second stacked structure comprises a plurality of conductive material layers and a plurality of insulating material layers alternately stacked;

a variable resistance pillar, disposed on the substrate and at a side of the first stacked structure opposite to the channel pillar; and

an electrode pillar, disposed on the substrate and located inside of the variable resistance pillar.

2. The three-dimensional resistive memory of claim 1, wherein the conductive material layers comprise TiN or TaN.

3. The three-dimensional resistive memory of claim 1, wherein the electrode pillar comprises, from outside to inside, an ion exchange layer, a barrier layer and an electrode layer.

4. The three-dimensional resistive memory of claim 3, wherein the ion exchange layer comprises Ti, Al or Ta.

5. The three-dimensional resistive memory of claim 3, wherein the barrier layer comprises titanium oxynitride or aluminum oxide.

6. The three-dimensional resistive memory of claim 3, wherein the electrode layer comprises TiN or TaN.

7. The three-dimensional resistive memory of claim 1, further comprising an insulating pillar disposed on the substrate and located inside of the channel pillar.

8. The three-dimensional resistive memory of claim 1, wherein a sidewall of the first stacked structure connected to the variable resistance pillar has a plurality of recesses, and one of the plurality of recesses is located between two adjacent conductive material layers or between two adjacent insulating material layers.

9. The three-dimensional resistive memory of claim 1, further comprising:

a bit line; and

a word line,

wherein the bit line is electrically connected to the electrode pillar, the word line is electrically connected to the first gate pillar, at least one of the bit line and the word line has an extension direction across an extension direction of the second stacked structure.

10. The three-dimensional resistive memory of claim 1, further comprising:

a second gate pillar, disposed on the substrate and at a fourth side of the channel pillar opposite to the first side; and

a second gate dielectric layer, disposed between the channel pillar and the second gate pillar.

11. The three-dimensional resistive memory of claim 10, further comprising:

a bit line; and

a word line,

wherein the bit line is electrically connected to the electrode pillar, the word line is electrically connected to the second gate pillar, and at least one of the bit line and the word line has an extension direction across an extension direction of the second stacked structure.

12. A three-dimensional resistive memory, comprising:

a stacked structure, disposed on the substrate and having a line portion and a protruding portion perpendicular to each other, wherein the stacked structure comprises a plurality of conductive material layers and a plurality of insulating material layers alternately stacked;

a first gate pillar, disposed on the substrate and at a first side of the protruding portion;

a first gate dielectric layer, disposed between the protruding portion and the first gate pillar;

a variable resistance pillar, disposed on the substrate and at a side of the protruding portion opposite to the line portion; and

an electrode pillar, disposed on the substrate and located inside of the variable resistance pillar.

13. The three-dimensional resistive memory of claim 12, wherein the conductive material layers comprise GaN or InGaAs.