Trench transistors and methods with low-voltage-drop shunt to body diode

• US 9,859,400 B2
• Filed: 04/02/2015
• Issued: 01/02/2018
• Est. Priority Date: 02/13/2012
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun, Blanchard, Richard A.
• Primary Examiner(s): Jahan, Bilkis
• Application Number:
  US14/677,511
• Publication Number:
  US 20150214336A1
• Time in Patent Office: 1,006 Days
• Field of Search: None
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7395 : Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7803 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming at least a first and a second trench gate electrode in a layer of first-conductivity-type semiconductor material;

performing one or more implants to thereby form body regions adjoining ones of said trench gate electrodes;

forming first-conductivity-type source regions above said body regions;

introducing ions into first portions of the body regions, adjoining the first trench gate electrode, but not into second portions of the body regions, adjoining the second trench gate electrode, to thereby lower a threshold voltage associated with the first body regions to make them different from a threshold voltage associated with the second body regions;

connecting the trench gate electrodes identically to a common gate electrode; and

connecting the source regions identically to a common source electrode.

2. The method of claim 1, further comprising forming at least one said trench gate electrode with a thick bottom oxide layer.

3. The method of claim 1, further comprising forming a second-conductivity-type shield region beneath at least one said trench gate electrode.

4. The method of claim 1, further comprising forming a trenched field plate between said trench gate electrodes.

5. The method of claim 1, whereby at least one said implant is performed as a masked implant.

6. The method of claim 1, whereby one said implant is performed as an unmasked implant.

7. The method of claim 1, wherein said first conductivity type is N type.

8. The method of claim 1, wherein said semiconductor material is silicon.

9. The device made by the method of claim 1.

10. The method of claim 1, wherein said step of introducing ions comprises implanting ions at interfaces between the first body regions and gate oxide regions associated with said first trench gate electrode;

wherein said ions are of a polarity which tends to deplete said body regions.

11. The method of claim 1, wherein said step of performing one or more implants comprises implanting first-conductivity-type dopants into the first body regions.

12. A method of manufacturing a semiconductor device, comprising:

forming at least a first and a second trench gate electrode in a layer of first-conductivity-type semiconductor material;

performing one or more implants of second-conductivity-type dopants to form body regions adjoining ones of said trench gate electrodes;

introducing ions into first portions of the body regions, adjoining the first trench gate electrode, but not into second portions of the body regions, adjoining the second trench gate electrode, to thereby lower a threshold voltage associated with the first body regions to make them different from a threshold voltage associated with the second body regions;

forming first-conductivity-type source regions above the body regions; and

shorting the first trench gate electrode, but not the second trench gate electrode, to said source regions.

13. The method of claim 12, further comprising forming at least one said trench gate electrode with a thick bottom oxide layer.

14. The method of claim 12, further comprising forming a second-conductivity-type shield region beneath at least one said trench gate electrode.

15. The method of claim 12, further comprising forming a trenched field plate between said trench gate electrodes.

16. The method of claim 12, wherein said first conductivity type is N type.

17. The method of claim 12, wherein said semiconductor material is silicon.

18. The device made by the method of claim 12.

19. The method of claim 12, wherein said step of introducing ions comprises implanting ions at interfaces between the first body regions and gate oxide regions associated with said first trench gate electrode;

wherein said ions are of a polarity which tends to deplete said second-conductivity-type body regions.

20. The method of claim 12, wherein said step of performing one or more implants comprises implanting first-conductivity-type dopants into the first body regions.