Method of forming trench semiconductor device having multiple trench depths

• US 9,859,449 B2
• Filed: 06/19/2017
• Issued: 01/02/2018
• Est. Priority Date: 03/06/2015
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Quddus, Mohammed Tanvir, Mudholkar, Mihir, Thomason, Michael
• Primary Examiner(s): Gupta, Raj R
• Application Number:
  US15/627,281
• Publication Number:
  US 20170288027A1
• Time in Patent Office: 197 Days
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A method of forming a semiconductor includes a providing a termination trench and an active trench within a semiconductor layer. The active trench is configured to be at a shallower depth than the termination trench to provide a trench depth difference. The selected trench depth difference in combination with one or more of the dopant concentration of the semiconductor layer, the thickness of the semiconductor layer, active trench width to termination trench width, and/or dopant profile of the semiconductor layer provide a semiconductor device having improved performance characteristics.

Claims

1. A method of forming a semiconductor device comprising:

providing a region of semiconductor material having a first conductivity type and a major surface;

forming a termination trench extending from a first portion of the major surface into the region of semiconductor material, wherein;

at least a portion of the termination trench extends to a first depth; and

the termination trench has a first width;

forming an active trench extending from a second portion of the major surface into the region of semiconductor material to a second depth, wherein;

the active trench has a second width less than the first width;

the first depth is greater than the second depth;

a portion of the region of semiconductor material is laterally interposed between the active trench and the termination trench in a cross-sectional view; and

the portion of the region of semiconductor material is devoid of trench structures whereby the active trench is a closest trench structure to the termination trench in the cross-sectional view;

forming a first conductive material having a first portion within the active trench and separated from the region of semiconductor material by a first dielectric region and a second portion within the termination trench separated from the region of semiconductor material by a second dielectric region; and

forming a second conductive material adjoining a third portion of the major surface, wherein the second conductive material is configured to provide a Schottky barrier.

2. The method of claim 1, wherein forming the termination trench and forming the active trench comprises providing the first depth greater than the second depth in a range greater than zero to approximately 3.0 microns.

3. The method of claim 1, wherein forming the termination trench and forming the active trench comprises providing the first depth greater than the second depth in a range greater than zero to approximately 2.0 microns.

4. The method of claim 1, wherein providing the region of semiconductor material comprises providing the region of semiconductor material comprising SiC.

5. The method of claim 1, wherein forming the termination trench and forming the active trench comprises providing a second width to first width ratio in a range from approximately 0.005 to approximately 0.125.

6. The method of claim 1, wherein forming the termination trench and forming the active trench comprises providing a second width to first width ratio that is less than or equal to approximately 0.03.

7. The method of claim 1, wherein:

providing the region of semiconductor comprises providing a semiconductor layer adjoining a semiconductor substrate such that the semiconductor layer defines the major surface;

providing the semiconductor layer comprises providing the semiconductor layer having a first dopant concentration; and

providing the semiconductor substrate comprising providing the semiconductor substrate having a second dopant concentration greater than the first dopant concentration.

8. The method of claim 7, wherein:

providing the semiconductor layer comprises providing the semiconductor layer having a thickness of approximately 1.5 microns to approximately 2.5 microns;

providing the first dopant concentration comprises providing the first dopant concentration in a range from approximately 1.0×

10¹⁶ atoms/cm³ and approximately 1.0×

10¹⁷ atoms/cm³; and

forming the termination trench and forming the active trench comprises providing the first depth greater than the second depth in a range greater than zero to approximately 2.0 microns.

9. The method of claim 7, wherein:

providing the semiconductor layer comprises providing the semiconductor layer having a thickness of approximately 2.25 microns to approximately 3.25 microns;

providing the first dopant concentration comprises providing the first dopant concentration in a range from approximately 1.5×

10¹⁶ atoms/cm³ and approximately 8.0×

10¹⁶ atoms/cm³; and

forming the termination trench and forming the active trench comprises providing the first depth greater than the second depth in a range greater than zero to approximately 1.8 microns.

10. The method of claim 7, wherein:

providing the semiconductor layer comprises providing the semiconductor layer having a thickness of approximately 2.7 microns to approximately 4.5 microns;

providing the first dopant concentration comprises providing the first dopant concentration in a range from approximately 1.0×

10¹⁶ atoms/cm³ and approximately 6.0×

10¹⁶ atoms/cm³; and

forming the termination trench and forming the active trench comprises providing the first depth greater than the second depth in a range greater than zero to approximately 1.5 microns.

11. The method of claim 7, wherein providing the semiconductor layer comprises providing the semiconductor layer having a non-uniform dopant profile.

12. The method of claim 7, wherein:

forming the termination trench and forming the active trench comprises providing the first depth greater than the second depth to define a trench depth difference; and

providing the semiconductor layer comprises providing the first dopant concentration of approximately 6.0×

10¹⁶ atoms/cm³ such that breakdown voltage of the semiconductor device is substantially constant over a range of trench depth difference between approximately 0.1 microns and approximately 1.0 microns.

13. The method of claim 1 further comprising providing a doped layer adjoining the third portion of the major surface adjacent to the second conductive material.

14. The method of claim 1 further comprising providing a doped region of a second conductivity type adjoining a side surface of the active trench.

15. The method of claim 1 further comprising forming a conductive layer electrically coupling the second conductive material to the first portion and the second portion of the first conductive material.

16. A method of forming a semiconductor device comprising:

providing a region of semiconductor material comprising a semiconductor layer adjoining a semiconductor substrate, the semiconductor layer defining a major surface, wherein the semiconductor layer has a first dopant concentration and the semiconductor substrate has a second dopant concentration greater than the first dopant concentration;

in a single step;

forming a termination trench extending from a first portion of the major surface into the region of semiconductor material, wherein the first trench extends to a first depth, and wherein the termination trench has a first width; and

forming a plurality of active trenches each extending from a second portion of the major surface into the region of semiconductor material to a second depth, wherein each active trench has a second width less than the first width, and wherein the first depth is greater than the second depth to define a trench depth difference, and wherein one of the active trenches is disposed in the region of semiconductor material as a closest trench structure to the termination trench;

forming a first conductive material within each active trench and separated from the region of semiconductor material by a dielectric region; and

forming a second conductive material having a first portion adjoining a third portion of the major surface, wherein the first portion of the second conductive material is configured to provide a Schottky barrier.

17. The method of claim 16, wherein:

forming the second conductive material comprises;

providing the second conductive material having a second portion adjoining the first conductive material; and

providing a gap laterally separating the first portion and the second portion of the second conductive material;

forming the first conductive material comprises forming the first conductive material in the termination trench separated from the region of semiconductor material by another dielectric region; and

the method further comprises forming a dielectric layer within the termination trench and overlapping the first conductive material within the termination trench and a portion of the major surface.

18. A method of forming a Schottky semiconductor device comprising:

providing a region of semiconductor material comprising a semiconductor layer adjacent a semiconductor substrate, the semiconductor layer defining a major surface, wherein the semiconductor layer has a first dopant concentration and the semiconductor substrate has a second dopant concentration greater than the first dopant concentration;

forming a termination trench extending from a first portion of the major surface into the region of semiconductor material, wherein;

the termination trench extends to a first depth; and

the termination trench has a first width;

forming an active trench extending from a second portion of the major surface into the region of semiconductor material to a second depth, wherein;

the active trench has a second width less than the first width;

the first depth is greater than the second depth to provide a trench depth difference;

a portion of the region of semiconductor material is laterally interposed between the active trench and the termination trench in a cross-sectional view; and

the portion of the region of semiconductor material is devoid of trench structures so that the active trench is a closest trench structure to the termination trench in the cross-sectional view;

forming a first conductive material within the second trench and separated from the region of semiconductor material by a dielectric region; and

forming a second conductive material adjoining a third portion of the major surface, wherein the second conductive material is configured to provide a Schottky barrier.

19. The method of claim 18 further comprising:

forming a conductive spacer along a sidewall surface of the termination trench, wherein the second conductive material is physically attached to the conductive spacer; and

forming a conductive layer disposed over the major surface electrically connected to the second conductive material.

20. The method of claim 18, wherein:

forming the termination trench and forming the active trench comprises;

providing a masking layer over the major surface, the masking layer having a termination trench opening and an active trench opening; and

in a single step, removing portions of the region of semiconductor material to form the termination trench and the active trench; and

the method further comprises providing a doped region adjoining a side surface of the active trench and having an opposite conductivity type to that of the semiconductor layer.