Half bridge power conversion circuits using GaN devices

• US 9,859,732 B2
• Filed: 03/24/2015
• Issued: 01/02/2018
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel M., Sharma, Santosh, Zhang, Ju Jason
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): O TOOLE, COLLEEN J
• Application Number:
  US14/667,319
• Publication Number:
  US 20160079844A1
• Time in Patent Office: 1,015 Days
• Field of Search: 327108-111, 327423, 327424, 327588
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02M 1/0048 : Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/088 : for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/155 : using semiconductor devices only
• CPC Class Codes: H02M 3/157 : with digital control
• CPC Class Codes: H02M 3/1584 : with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1588 : comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/102 : in field-effect transistor switches
• CPC Class Codes: H03K 19/018507 : Interface arrangements
• CPC Class Codes: H03K 3/012 : Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356017 : using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: Y02B 40/00 : Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Claims

1. A half bridge circuit comprising:

a GaN-based low side circuit disposed on a first monolithic die, and including;

a GaN-based low side switch having a low side switch control gate, a low side switch source and a low side switch drain, wherein the low side switch source is connected to a ground and the low side switch drain is connected to a switch node;

a GaN-based low side switch driver having an output connected to the low side switch control gate; and

a GaN-based level shift circuit having an input and an output; and

a GaN-based high side circuit disposed on a second monolithic die, and including;

a GaN-based high side switch having a high side control gate, a high side switch source and a high side switch drain, wherein the high side switch source is connected to the switch node and the high side switch drain is connected to a voltage source; and

a GaN-based high side switch driver having an output connected to the high side switch control gate and an input connected to the output of the GaN-based level shift circuit;

wherein the GaN-based level shift circuit is configured to send a level shift signal from the first monolithic die to the second monolithic die.

2. The half bridge circuit of claim 1 further comprising a low side control circuit coupled to the high side and the low side switch drivers.

3. The half bridge circuit of claim 2 wherein the low side control circuit is disposed on the second monolithic die and further comprises the level shift circuit.

4. The half bridge circuit of claim 3 wherein the GaN-based high side switch driver includes a level shift receiver coupled to the level shift circuit, and the level shift receiver includes a signal modulator that is coupled to the high side switch driver.

5. The half bridge circuit of claim 3 wherein the level shift circuit includes an inverter having a resistor pull up and a pull down transistor.

6. The half bridge circuit of claim 1 further comprising one or more pulse generators.

7. The half bridge circuit of claim 1 wherein at least one of the GaN-based low side switch driver and the GaN-based high side switch driver have at least one delay circuit.

8. The half bridge circuit of claim 1 wherein the GaN-based low side circuit includes a startup circuit.

9. The half bridge circuit of claim 1 further comprising a shoot through protection circuit configured to prevent simultaneous conduction of the GaN-based high side and low side switches.

10. The half bridge circuit of claim 1 wherein the GaN-based high side circuit includes a high side controller coupled to the GaN-based high side switch driver;

and

the GaN-based low side circuit includes a low side controller coupled to the GaN-based low side switch driver and the high side controller.

11. The half bridge circuit of claim 1 wherein at least one of the GaN-based low side circuit and the GaN-based high side circuit have an ESD clamp circuit.