Synchronous rectifier design for wireless power receiver
First Claim
1. A receiver comprising:
- an antenna configured to receive power transmission waves; and
a synchronous rectifier coupled to the antenna and configured to synchronously rectify an alternating current (AC) voltage of the power transmission waves to generate a direct current (DC) voltage, wherein the synchronous rectifier includes;
a first rectifying diode that includes a first anode terminal and a first cathode terminal, wherein the first rectifying diode is configured to receive a first portion of the AC voltage that has a positive polarity;
a second rectifying diode that includes a second anode terminal and a second cathode terminal, wherein the second rectifying diode is configured to receive a second portion of the AC voltage that has a negative polarity;
a first transistor that includes a first source terminal, a first drain terminal, and a first gate terminal, wherein the first anode and the first cathode terminals are connected to the first transistor;
a second transistor that includes a second source terminal, a second drain terminal, and a second gate terminal, wherein the second anode and the second cathode terminals are connected to the second transistor; and
circuitry that is configured to introduce a timing delay between driving the first and second transistors;
a first boost converter in electrical communication with the synchronous rectifier, the first boost converter configured to match an impedance of a load associated with the receiver.
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Accused Products
Abstract
Synchronous rectifier circuit topologies for a wireless power receiver receiving a supply of power from a wireless transmitter are disclosed. The synchronous rectifier circuit topologies include a half-bridge diode-FET transistor rectifier for rectifying the wireless power into power including a DC waveform, using a control scheme that may be provided by a delay-locked loop clock, or phase shifters, or wavelength links to control conduction of FET transistors in the synchronous rectifier circuit topology, and maintaining a constant switching frequency to have the diodes, coupled to FET transistors, to allow current to flow through each one respectively at the appropriate timing, focusing on high conduction times. The synchronous rectifier circuit topologies may enable power transfer of high-frequency signals at enhanced efficiency due to significant reduction of forward voltage drop and lossless switching.
829 Citations
19 Claims
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1. A receiver comprising:
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an antenna configured to receive power transmission waves; and a synchronous rectifier coupled to the antenna and configured to synchronously rectify an alternating current (AC) voltage of the power transmission waves to generate a direct current (DC) voltage, wherein the synchronous rectifier includes; a first rectifying diode that includes a first anode terminal and a first cathode terminal, wherein the first rectifying diode is configured to receive a first portion of the AC voltage that has a positive polarity; a second rectifying diode that includes a second anode terminal and a second cathode terminal, wherein the second rectifying diode is configured to receive a second portion of the AC voltage that has a negative polarity; a first transistor that includes a first source terminal, a first drain terminal, and a first gate terminal, wherein the first anode and the first cathode terminals are connected to the first transistor; a second transistor that includes a second source terminal, a second drain terminal, and a second gate terminal, wherein the second anode and the second cathode terminals are connected to the second transistor; and circuitry that is configured to introduce a timing delay between driving the first and second transistors; a first boost converter in electrical communication with the synchronous rectifier, the first boost converter configured to match an impedance of a load associated with the receiver. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for receiving wireless power, the method comprising:
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receiving, by an antenna of a receiver, power transmission waves; rectifying, by a synchronous rectifier of the receiver, an alternating current (AC) voltage of the power transmission waves to generate a direct current (DC) voltage; and matching, by a first boost converter that is in electrical communication with the synchronous rectifier, an impedance of a load associated with the receiver, and wherein the synchronous rectifier includes; a first rectifying diode that includes a first anode terminal and a first cathode terminal, wherein the first rectifying diode is configured to receive a first portion of the AC voltage that has a positive polarity; a second rectifying diode that includes a second anode terminal and a second cathode terminal, wherein the second rectifying diode is configured to receive a second portion of the AC voltage that has a negative polarity; a first transistor that includes a first source terminal, a first drain terminal, and a first gate terminal, wherein the first anode and the first cathode terminals are connected to the first transistor; a second transistor that includes a second source terminal, a second drain terminal, and a second gate terminal, wherein the second anode and the second cathode terminals are connected to the second transistor; and circuitry that is configured to introduce a timing delay between driving the first and second transistors. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification