Buffer with programmable input/output phase relationship

• US 9,859,901 B1
• Filed: 03/08/2016
• Issued: 01/02/2018
• Est. Priority Date: 03/08/2016
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Chu, Min, Hsu, John C., Wade, Ron D.
• Primary Examiner(s): Houston, Adam
• Application Number:
  US15/064,369
• Time in Patent Office: 665 Days
• Field of Search: 327147-149, 327156-158
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00

Abstract

An apparatus includes a phase locked loop circuit having a phase comparator for generating a signal indicative of a phase difference between a signal presented to a first input of the phase comparator and a signal presented to a second input of the phase comparator. The apparatus includes at least one delay element disposed so as to enable contributing at least one of the following:

• • i) delay to a signal provided to the first input of the phase comparator;
  • ii) delay to a signal provided to the second input of the phase comparator.
    A delay contributed by the at least one delay element varies in accordance with an associated delay control value. The phase locked loop circuit and the at least one delay element reside on a same semiconductor substrate.

Claims

1. An apparatus comprising:

a phase locked loop circuit including a phase comparator for generating a signal indicative of a phase difference between a signal presented to a first input of the phase comparator and a signal presented to a second input of the phase comparator;

a first delay element for contributing delay to the signal provided to the first input of the phase comparator;

a second delay element for contributing delay to the signal provided to the second input of the phase comparator, wherein a delay contributed by at least one of the first delay element and the second delay element varies in accordance with an associated delay control value; and

a microcontroller coupled to the first delay element and to the second delay element, wherein the microcontroller generates the associated delay control value, wherein the phase locked loop circuit, the first delay element, the second delay element and the microcontroller reside on a same semiconductor substrate.

2. The apparatus of claim 1 wherein the first delay element contributes an analog delay corresponding to the associated delay control value.

3. The apparatus of claim 1 wherein the first delay element contributes a fixed delay corresponding to its associated delay control value.

4. The apparatus of claim 1 further comprising:

a nonvolatile memory for storing the associated delay control value, wherein the nonvolatile memory resides on the same semiconductor substrate.

5. The apparatus of claim 1 wherein the first delay element is a programmable delay element that receives the associated delay control value as a digital signal.

6. The apparatus of claim 5 wherein the first delay element contributes an analog delay corresponding to the associated delay control value.

7. An apparatus comprising:

a phase locked loop circuit including a phase comparator for generating a signal indicative of a phase difference between a signal presented to a first input of the phase comparator and a signal presented to a second input of the phase comparator;

at least one delay element disposed so as to enable contributing delay to the signal provided to the first input of the phase comparator and delay to the signal provided to the second input of the phase comparator, the at least one delay element including a first delay element coupling the first input of the phase comparator to a feedback loop of the phase locked loop circuit, wherein a delay contributed by the first delay element varies in accordance with an associated delay control value; and

a microcontroller residing on the same semiconductor substrate as the phase locked loop circuit and the at least one delay element, wherein the microcontroller generates the associated delay control value.

8. The apparatus of claim 7 wherein the first delay element receives the associated delay control value as a digital signal.

9. The apparatus of claim 8 wherein the first delay element contributes an analog delay corresponding to the associated delay control value.

10. An apparatus comprising:

a phase locked loop circuit including a phase comparator for generating a signal indicative of a phase difference between a signal presented to a first input of the phase comparator and a signal presented to a second input of the phase comparator, wherein the phase comparator comprises a time-to-digital converter;

a first delay element coupling the first input of the phase comparator to a feedback loop of the phase locked loop circuit, wherein a delay contributed by the first delay element varies in accordance with a first delay control value; and

a second delay element coupled to contribute a delay to the signal provided to the second input of the phase comparator, wherein the delay contributed by the second delay element varies in accordance with a second delay control value, and wherein the first delay element, the second delay element and the phase locked loop circuit reside on a semiconductor substrate.

11. The apparatus of claim 10 further comprising:

a microcontroller residing on the same semiconductor substrate, wherein the microcontroller generates the first delay control value and the second delay control value; and

a nonvolatile memory for storing the first delay control value and the second delay control value, wherein the nonvolatile memory resides on the semiconductor substrate.

12. A method of controlling an input/output phase relationship of a phase locked loop circuit comprising the steps of:

receiving an output clock signal of a phase locked loop at a first programmable delay element, the first programmable delay element enabled for contributing delay to the output clock signal to generate a signal provided to a first input of a phase comparator;

receiving an input reference clock signal at a second programmable delay element, the second programmable delay element disposed so as to enable contributing delay to the input reference clock signal to generate a signal provided to a second input of the phase comparator;

comparing the signal provided to a first input of a phase comparator to the signal provided to a second input of a phase comparator to identify a phase error signal, wherein the phase comparator is a time-to-digital converter;

filtering the phase error signal to generate a filtered phase error signal;

generating a fast clock signal at a digitally controlled oscillator using the filtered phase error signal; and

dividing the fast clock signal to generate the output clock signal.

13. The method of claim 12 wherein the phase error signal comprises a detected phase error value.