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Ultra low power wideband non-coherent binary phase shift keying demodulator using first order sideband filters with phase zero alignment

  • US 9,860,098 B2
  • Filed: 02/24/2017
  • Issued: 01/02/2018
  • Est. Priority Date: 08/25/2014
  • Status: Active Grant
First Claim
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1. An ultra low power wideband non-coherent binary phase shift keying (BPSK) demodulation circuit using first order sideband filters with phase zero alignment, the ultra low power wideband non-coherent BPSK demodulation circuit comprises:

  • a sideband separation and upper sideband signal delay unit to output a lower sideband analog signal and a phase delayed analog signal to be delayed with preset phase from upper sideband analog signal, when a modulation signal in the input of the unit is divided to an upper sideband and a lower sideband by 1st order filters whose cutoff frequency is same as carrier frequency;

    a data demodulation unit to demodulate digital data through a hysteresis circuit that latches an analog pulse signal to appear in the phase changing edge of BPSK modulation signal, in accordance with a phase difference between the lower sideband analog signal and the phase delayed analog signal being set to phase 0°

    ; and

    a data clock recovery unit to recover data clock using a digitized signal from the lower sideband analog signal and the demodulated digital data,wherein the sideband separation and upper sideband signal delay unit comprises;

    a 1st order low-pass filter (1st order LPF) whose cutoff frequency is the same as carrier frequency, configured to isolate lower sideband from the modulation signal;

    a 1st order high-pass filter (1st order HPF) whose cutoff frequency is the same as carrier frequency, configured to isolate upper sideband from the modulation signal; and

    a delay circuit to delay with preset phase from upper sideband analog signal that is the output of the 1st order HPF,wherein the data demodulation unit comprises;

    a subtracter to generate an analog pulse signal to appear in the phase changing edge of the modulation signal, the edge being caused by the difference of analog signals which are the lower sideband analog signal and the phase delayed analog signal in accordance with the phase difference between the analog signals being set to phase 0°

    ; and

    a Schmitt trigger that is a hysteresis circuit to demodulate digital data by latching the analog pulse signal,wherein the data clock recovery unit comprises;

    a comparator to digitize from the lower sideband analog signal; and

    an exclusive-NOR gate to compare the digitized lower sideband analog signal with the demodulated digital data signal, andwherein the upper sideband analog signal that is from the output of 1st order filter, occurs faster than the lower sideband analog signal by π

    /2 or ¼

    period of carrier frequency, and the phase delayed analog signal occurs through the delay circuit to delay π

    /2 or ¼

    period of carrier frequency for finding phase changing edge with aligning phase 0°

    difference between the phase delayed analog signal and the lower sideband analog signal.

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