Ultra low power wideband non-coherent binary phase shift keying demodulator using first order sideband filters with phase zero alignment

• US 9,860,098 B2
• Filed: 02/24/2017
• Issued: 01/02/2018
• Est. Priority Date: 08/25/2014
• Status: Active Grant

• Current Assignee: Benjamin P. Wilkerson
• Original Assignee: Benjamin P. Wilkerson
• Inventors: Wilkerson, Benjamin P.
• Primary Examiner(s): Huang, David S
• Application Number:
  US15/441,946
• Publication Number:
  US 20170171007A1
• Time in Patent Office: 312 Days
• CPC Class Codes: H04B 1/71637 Receiver aspects H04B1/7183 takes precedence
• CPC Class Codes: H04B 2201/71636 Transmitted reference
• CPC Class Codes: H04L 2027/0036 using a recovered symbol clock
• CPC Class Codes: H04L 27/0014 Carrier regulation of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657
• CPC Class Codes: H04L 27/2331 wherein the received signal is demodulated using one or more delayed versions of itself
• CPC Class Codes: H04L 27/2334 using filters
• CPC Class Codes: H04L 27/2335 using temporal properties of the received signal
• CPC Class Codes: H04L 7/0278 Band edge detection

Abstract

An embodiment of the present invention relates to an ultra low power wideband asynchronous binary phase shift keying (BPSK) demodulation method and a circuit configuration thereof. The ultra low power wideband asynchronous BPSK demodulation circuit comprises a sideband division and upper sideband signal delay unit dividing a modulated signal into an upper sideband and a lower sideband by a first order high-pass filter and a first order low-pass filter; a data demodulation unit latching, through a hysteresis circuit, a signal generated by a difference between the analog signals in which a phase difference between the delayed upper sideband analog signal and the lower sideband analog signal is aligned at 0°, so as to demodulate digital data; and a data clock recovery unit for generating a data clock by using a signal digitalized from the lower sideband analog signal through a comparator and a data signal.

Claims

1. An ultra low power wideband non-coherent binary phase shift keying (BPSK) demodulation circuit using first order sideband filters with phase zero alignment, the ultra low power wideband non-coherent BPSK demodulation circuit comprises:

a sideband separation and upper sideband signal delay unit to output a lower sideband analog signal and a phase delayed analog signal to be delayed with preset phase from upper sideband analog signal, when a modulation signal in the input of the unit is divided to an upper sideband and a lower sideband by 1^st order filters whose cutoff frequency is same as carrier frequency;

a data demodulation unit to demodulate digital data through a hysteresis circuit that latches an analog pulse signal to appear in the phase changing edge of BPSK modulation signal, in accordance with a phase difference between the lower sideband analog signal and the phase delayed analog signal being set to phase 0°

; and

a data clock recovery unit to recover data clock using a digitized signal from the lower sideband analog signal and the demodulated digital data,

wherein the sideband separation and upper sideband signal delay unit comprises;

a 1^st order low-pass filter (1^st order LPF) whose cutoff frequency is the same as carrier frequency, configured to isolate lower sideband from the modulation signal;

a 1^st order high-pass filter (1^st order HPF) whose cutoff frequency is the same as carrier frequency, configured to isolate upper sideband from the modulation signal; and

a delay circuit to delay with preset phase from upper sideband analog signal that is the output of the 1^st order HPF,

wherein the data demodulation unit comprises;

a subtracter to generate an analog pulse signal to appear in the phase changing edge of the modulation signal, the edge being caused by the difference of analog signals which are the lower sideband analog signal and the phase delayed analog signal in accordance with the phase difference between the analog signals being set to phase 0°

; and

a Schmitt trigger that is a hysteresis circuit to demodulate digital data by latching the analog pulse signal,

wherein the data clock recovery unit comprises;

a comparator to digitize from the lower sideband analog signal; and

an exclusive-NOR gate to compare the digitized lower sideband analog signal with the demodulated digital data signal, and

wherein the upper sideband analog signal that is from the output of 1^st order filter, occurs faster than the lower sideband analog signal by π

/2 or ¼

period of carrier frequency, and the phase delayed analog signal occurs through the delay circuit to delay π

/2 or ¼

period of carrier frequency for finding phase changing edge with aligning phase 0°

difference between the phase delayed analog signal and the lower sideband analog signal.

2. The ultra low power wideband non-coherent BPSK demodulation circuit of claim 1, wherein the sideband separation and upper sideband signal delay unit comprises a 1^st order HPF that isolates upper sideband, a 1^st order LPF that isolates lower sideband, and a delay circuit, wherein the output of the 1^st order HPF whose cutoff frequency is the same as carrier frequency, is an upper sideband analog signal that is π

/4 or ⅛

period faster than the BPSK modulation signal, and a delayed upper sideband analog signal that is generated by the delay circuit to delay π

/2 or ¼

period of carrier frequency from the upper sideband analog signal, is π

/4 or ⅛

period slower than the BPSK modulation signal, and the output of the 1^st order LPF whose cutoff frequency is the same as carrier frequency, is a lower sideband analog signal that is π

/4 or ⅛

period slower than the BPSK modulation signal, and

wherein the phase changing edge of the BPSK modulation signal in the phase 0°

difference between the phase delayed analog signal and the lower sideband analog signal is found in stable by a phase difference between the 1^st order HPF'"'"'s output signal and the 1^st order LPF'"'"'s output signal being maintained to π

/2 in a range from upper sideband to lower sideband, and the phase delayed analog signal being aligned to the lower sideband analog signal with phase 0°

difference.

3. The ultra low power wideband non-coherent BPSK demodulation circuit of claim 1, wherein the data demodulation unit comprises a subtracter and a Schmitt trigger that is a hysteresis circuit,

wherein digital data is demodulated by latching an analog pulse signal that consists of positive and negative pulses which appear in phase changing edge based on difference of analog signals, by aligning in phase 0°

difference between the phase delayed analog signal and the lower sideband analog signal.

4. The ultra low power wideband non-coherent BPSK demodulation circuit of claim 1, wherein the data clock recovery unit comprises a comparator and an exclusive-NOR gate,

wherein a data clock is recovered through the calculation of the exclusive-NOR gate with the digital data signal and a digital to be digitized from the lower sideband analog signal.

5. An ultra low power wideband non-coherent binary phase shift keying (BPSK) demodulation method using first order sideband filters with phase zero alignment, the ultra low power wideband non-coherent BPSK demodulation method comprises:

a sideband separation and upper sideband signal delay step to output a lower sideband analog signal and a phase delayed analog signal to be delayed with preset phase from upper sideband analog signal, when a modulation signal in the input of the stage is divided to an upper sideband and a lower sideband by 1^st order filters whose cutoff frequency is same as carrier frequency;

a data demodulation step to demodulate digital data through a hysteresis circuit that latches an analog pulse signal to appear in the phase changing edge of BPSK modulation signal, in accordance with a phase difference between the lower sideband analog signal and the phase delayed analog signal being set to phase 0°

; and

a data clock recovery step to recover data clock using a digitized signal from the lower sideband analog signal and above demodulated digital data,

wherein the sideband separation and upper sideband signal delay step comprises;

a step to isolate lower sideband from the modulation signal by a 1^st order low-pass filter (1^st order LPF) whose cutoff frequency is the same as carrier frequency;

a step to isolate upper sideband from the modulation signal by 1^st order high-pass filter (1^st order HPF) whose cutoff frequency is the same as carrier frequency; and

a delay step to delay with preset phase from upper sideband analog signal that is the output of the 1^st order HPF,

the data demodulation step comprises;

a step to generate an analog pulse signal to appear in the phase changing edge of the modulation signal by a subtracter, and the edge is caused by the difference of analog signals which are the lower sideband analog signal and the delayed upper sideband analog signal because the phase difference between the analog signals is set to phase 0°

; and

a step to demodulate digital data through latching the analog pulse signal by a Schmitt trigger that is a hysteresis circuit,

wherein the data clock recovery step comprises;

a step to convert a digital signal from the lower sideband analog signal by a comparator; and

a step to recover a data clock for comparing the converted lower sideband analog signal with the demodulated digital data by an exclusive-NOR gate, and

wherein the upper sideband analog signal that is from the output of 1^st order filter, occurs faster than the lower sideband analog signal by π

/2 or ¼

period of carrier frequency, and the phase delayed analog signal occurs through the delay circuit to delay π

/2 or ¼

period of carrier frequency for finding phase changing edge with aligning phase 0°

difference between the phase delayed analog signal and the lower sideband analog signal.